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Update length of control bus

This commit is contained in:
mrg 2020-09-15 09:49:00 -07:00
parent f25b6ffa61
commit aff3cd2aab
1 changed files with 2 additions and 2 deletions
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4
compiler/modules/bank.py
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@ -680,7 +680,7 @@ class bank(design.design):
# 2 pitches on the right for vias/jogs to access the inputs # 2 pitches on the right for vias/jogs to access the inputs
control_bus_offset = vector(-self.m3_pitch * self.num_control_lines[0] - 2 * self.m3_pitch, self.min_y_offset) control_bus_offset = vector(-self.m3_pitch * self.num_control_lines[0] - 2 * self.m3_pitch, self.min_y_offset)
# The control bus is routed up to two pitches below the bitcell array # The control bus is routed up to two pitches below the bitcell array
control_bus_length = self.port_data[0].height control_bus_length = self.port_data_inst[0].uy() - self.min_y_offset
self.bus_pins[0] = self.create_bus(layer="m2", self.bus_pins[0] = self.create_bus(layer="m2",
offset=control_bus_offset, offset=control_bus_offset,
names=self.control_signals[0], names=self.control_signals[0],
@ -692,7 +692,7 @@ class bank(design.design):
# Port 1 # Port 1
if len(self.all_ports)==2: if len(self.all_ports)==2:
# The other control bus is routed up to two pitches above the bitcell array # The other control bus is routed up to two pitches above the bitcell array
control_bus_length = self.port_data[1].height control_bus_length = self.max_y_offset - self.port_data_inst[1].by()
control_bus_offset = vector(self.bitcell_array_right + 2.5 * self.m3_pitch, control_bus_offset = vector(self.bitcell_array_right + 2.5 * self.m3_pitch,
self.max_y_offset - control_bus_length) self.max_y_offset - control_bus_length)
# The bus for the right port is reversed so that the rbl_wl is closest to the array # The bus for the right port is reversed so that the rbl_wl is closest to the array