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power ring routing optimized, stretch crba pins to edge of power ring to avoid drc errors

This commit is contained in:
Jesse Cirimelli-Low 2026-05-13 12:35:08 -07:00
parent 34b317ce7d
commit afca50c20b
2 changed files with 19 additions and 9 deletions
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11
compiler/base/hierarchy_layout.py
View File

@ -2228,11 +2228,14 @@ class layout():
left/right/top/bottom vdd/gnd center offsets for use in other left/right/top/bottom vdd/gnd center offsets for use in other
modules.. modules..
""" """
[ll, ur] = self.bbox [ll, ur] = self.bbox
supply_rail_spacing = self.supply_rail_pitch supply_rail_spacing = self.supply_rail_pitch
height = (ur.y - ll.y) + 3 * self.supply_rail_pitch - supply_rail_spacing
width = (ur.x - ll.x) + 3 * self.supply_rail_pitch - supply_rail_spacing #ll = ll - vector(self.supply_rail_pitch, self.supply_rail_pitch)
#ur = ur - vector(self.supply_rail_pitch, self.supply_rail_pitch)
height = (ur.y - ll.y) + 2 * self.supply_rail_pitch
width = (ur.x - ll.x) + 2 * self.supply_rail_pitch
# LEFT vertical rails # LEFT vertical rails
if left: if left:

17
compiler/modules/capped_replica_bitcell_array.py
View File

@ -233,9 +233,14 @@ class capped_replica_bitcell_array(bitcell_base_array):
ll = vector(-1 * self.dummy_col_insts[0].width, -1 * self.dummy_row_insts[0].height) ll = vector(-1 * self.dummy_col_insts[0].width, -1 * self.dummy_row_insts[0].height)
self.translate_all(ll) self.translate_all(ll)
self.capped_rba_width = self.dummy_col_insts[0].width + self.dummy_row_insts[0].width + self.dummy_col_insts[1].width
self.capped_rba_height = self.dummy_col_insts[0].height self.capped_rba_width = (self.dummy_col_insts[0].width
+ self.replica_bitcell_array_inst.width
+ self.dummy_col_insts[1].width)
self.capped_rba_height = (self.dummy_row_insts[0].height
+ self.replica_bitcell_array_inst.height
+ self.dummy_row_insts[1].height)
self.route_power_ring(self.supply_stack[2], self.supply_stack[0]) self.route_power_ring(self.supply_stack[2], self.supply_stack[0])
self.route_supplies() self.route_supplies()
@ -325,6 +330,8 @@ class capped_replica_bitcell_array(bitcell_base_array):
self.dummy_col_insts[1].place(offset=offset) self.dummy_col_insts[1].place(offset=offset)
def add_layout_pins(self): def add_layout_pins(self):
self.pin_width = self.capped_rba_width + 4 * self.supply_rail_pitch
self.pin_height = self.capped_rba_height + 4 * self.supply_rail_pitch
for pin_name in self.used_wordline_names + self.bitline_pin_list: for pin_name in self.used_wordline_names + self.bitline_pin_list:
pin = self.replica_bitcell_array_inst.get_pin(pin_name) pin = self.replica_bitcell_array_inst.get_pin(pin_name)
@ -332,13 +339,13 @@ class capped_replica_bitcell_array(bitcell_base_array):
if "wl" in pin_name: if "wl" in pin_name:
# wordlines # wordlines
pin_offset = pin.ll().scale(0, 1) pin_offset = pin.ll().scale(0, 1)
pin_width = self.capped_rba_width pin_width = self.pin_width
pin_height = pin.height() pin_height = pin.height()
else: else:
# bitlines # bitlines
pin_offset = pin.ll().scale(1, 0) pin_offset = pin.ll().scale(1, 0)
pin_width = pin.width() pin_width = pin.width()
pin_height = self.capped_rba_height pin_height = self.pin_height
self.add_layout_pin(text=pin_name, self.add_layout_pin(text=pin_name,
layer=pin.layer, layer=pin.layer,