Merge branch 'dev' into add_wmask

compiler/modules/bank.py

@@ -30,7 +30,7 @@ class bank(design.design):
 
         self.sram_config = sram_config
         sram_config.set_local_config(self)
-        if self.write_size is not None:
+        if self.write_size:
             self.num_wmasks = int(self.word_size/self.write_size)
         else:
             self.num_wmasks = 0
@@ -722,7 +722,7 @@ class bank(design.design):
             din_name = "din{0}_{1}".format(port,row)
             self.copy_layout_pin(self.port_data_inst[port], data_name, din_name)
 
-        if self.word_size is not None:
+        if self.word_size:
             for row in range(self.num_wmasks):
                 wmask_name = "bank_wmask_{}".format(row)
                 bank_wmask_name = "bank_wmask{0}_{1}".format(port, row)

compiler/modules/multibank.py

@@ -65,11 +65,11 @@ class multibank(design.design):
     def add_pins(self):
         """ Adding pins for Bank module"""
         for i in range(self.word_size):
-            self.add_pin("DOUT_{0}".format(i),"OUT")
+            self.add_pin("dout_{0}".format(i),"OUT")
         for i in range(self.word_size):
-            self.add_pin("BANK_DIN_{0}".format(i),"IN")
+            self.add_pin("bank_din_{0}".format(i),"IN")
         for i in range(self.addr_size):
-            self.add_pin("A_{0}".format(i),"INPUT")
+            self.add_pin("a_{0}".format(i),"INPUT")
 
         # For more than one bank, we have a bank select and name
         # the signals gated_*.
@@ -187,7 +187,7 @@ class multibank(design.design):
                                                         words_per_row=self.words_per_row)
         self.add_mod(self.sense_amp_array)
 
-        if self.write_size is not None:
+        if self.write_size:
             self.write_mask_driver_array = self.mod_write_mask_driver_array(columns=self.num_cols,
                                                                   word_size=self.word_size,
                                                                   write_size=self.write_size)
@@ -302,7 +302,7 @@ class multibank(design.design):
 
         temp = []
         for i in range(self.word_size):
-            temp.append("BANK_DIN_{0}".format(i))
+            temp.append("bank_din_{0}".format(i))
         for i in range(self.word_size):            
             if (self.words_per_row == 1):            
                 temp.append("bl_{0}".format(i))
@@ -325,7 +325,7 @@ class multibank(design.design):
         for i in range(self.word_size):
             temp.append("sa_out_{0}".format(i))
         for i in range(self.word_size):
-            temp.append("DOUT_{0}".format(i))
+            temp.append("dout_{0}".format(i))
         temp.extend([self.prefix+"tri_en", self.prefix+"tri_en_bar", "vdd", "gnd"])
         self.connect_inst(temp)
 
@@ -596,7 +596,7 @@ class multibank(design.design):
         """ Add pins for the sense amp output """
         for i in range(self.word_size):
             data_pin = self.sense_amp_array_inst.get_pin("data_{}".format(i))
-            self.add_layout_pin_rect_center(text="DOUT_{}".format(i),
+            self.add_layout_pin_rect_center(text="dout_{}".format(i),
                                             layer=data_pin.layer, 
                                             offset=data_pin.center(),
                                             height=data_pin.height(),
@@ -606,7 +606,7 @@ class multibank(design.design):
         """ Metal 3 routing of tri_gate output data """
         for i in range(self.word_size):
             data_pin = self.tri_gate_array_inst.get_pin("out_{}".format(i))
-            self.add_layout_pin_rect_center(text="DOUT_{}".format(i),
+            self.add_layout_pin_rect_center(text="dout_{}".format(i),
                                             layer=data_pin.layer, 
                                             offset=data_pin.center(),
                                             height=data_pin.height(),
@@ -619,8 +619,8 @@ class multibank(design.design):
         # Create inputs for the row address lines
         for i in range(self.row_addr_size):
             addr_idx = i + self.col_addr_size
-            decoder_name = "A_{}".format(i)
-            addr_name = "A_{}".format(addr_idx)
+            decoder_name = "a_{}".format(i)
+            addr_name = "a_{}".format(addr_idx)
             self.copy_layout_pin(self.row_decoder_inst, decoder_name, addr_name)
             
             
@@ -629,7 +629,7 @@ class multibank(design.design):
         
         for i in range(self.word_size):
             data_name = "data_{}".format(i)            
-            din_name = "BANK_DIN_{}".format(i)
+            din_name = "bank_din_{}".format(i)
             self.copy_layout_pin(self.write_driver_array_inst, data_name, din_name)
                         
 
@@ -668,7 +668,7 @@ class multibank(design.design):
             decode_names = ["Zb", "Z"]
             
             # The Address LSB
-            self.copy_layout_pin(self.col_decoder_inst, "A", "A[0]") 
+            self.copy_layout_pin(self.col_decoder_inst, "A", "a[0]") 
             
         elif self.col_addr_size > 1:
             decode_names = []
@@ -677,7 +677,7 @@ class multibank(design.design):
 
             for i in range(self.col_addr_size):
                 decoder_name = "in_{}".format(i)
-                addr_name = "A_{}".format(i)
+                addr_name = "a_{}".format(i)
                 self.copy_layout_pin(self.col_decoder_inst, decoder_name, addr_name)
                 
 
@@ -827,4 +827,4 @@ class multibank(design.design):
                      rotate=90)
         self.add_via(layers=("metal2","via2","metal3"),
                      offset=in_pin + self.m2m3_via_offset,
-                     rotate=90)
+                     rotate=90)

compiler/modules/port_data.py

@@ -22,7 +22,7 @@ class port_data(design.design):
         
         sram_config.set_local_config(self)
         self.port = port
-        if self.write_size is not None:
+        if self.write_size:
             self.num_wmasks = int(self.word_size/self.write_size)
         else:
             self.num_wmasks = 0
@@ -58,7 +58,7 @@ class port_data(design.design):
 
         if self.write_driver_array:
             self.create_write_driver_array()
-            if self.write_size is not None:
+            if self.write_size:
                 self.create_write_mask_and_array()
             else:
                 self.write_mask_and_array_inst = None
@@ -187,7 +187,7 @@ class port_data(design.design):
                                                      word_size=self.word_size,
                                                      write_size=self.write_size)
             self.add_mod(self.write_driver_array)
-            if self.write_size is not None:
+            if self.write_size:
                 self.write_mask_and_array = factory.create(module_type="write_mask_and_array",
                                                            columns=self.num_cols,
                                                            word_size=self.word_size,
@@ -320,7 +320,7 @@ class port_data(design.design):
                 temp.append(self.bl_names[self.port] + "_out_{0}".format(bit))
                 temp.append(self.br_names[self.port] + "_out_{0}".format(bit))
 
-        if self.write_size is not None:
+        if self.write_size:
             for i in range(self.num_wmasks):
                 temp.append("wdriver_sel_{}".format(i))
         else:

compiler/modules/write_driver_array.py

@@ -30,7 +30,7 @@ class write_driver_array(design.design):
         self.write_size = write_size
         self.words_per_row = int(columns / word_size)
 
-        if self.write_size is not None:
+        if self.write_size:
             self.num_wmasks = int(self.word_size/self.write_size)
 
         self.create_netlist()
@@ -62,7 +62,7 @@ class write_driver_array(design.design):
         for i in range(self.word_size):            
             self.add_pin("bl_{0}".format(i), "OUTPUT")
             self.add_pin("br_{0}".format(i), "OUTPUT")
-        if self.write_size is not None:
+        if self.write_size:
             for i in range(self.num_wmasks):
                 self.add_pin("en_{0}".format(i), "INPUT")
         else:
@@ -88,7 +88,7 @@ class write_driver_array(design.design):
             self.driver_insts[index]=self.add_inst(name=name,
                                                    mod=self.driver)
 
-            if self.write_size is not None:
+            if self.write_size:
                 self.connect_inst(["data_{0}".format(index),
                                    "bl_{0}".format(index),
                                    "br_{0}".format(index),
@@ -148,7 +148,7 @@ class write_driver_array(design.design):
                     self.add_layout_pin_rect_center(text=n,
                                                     layer="metal3",
                                                     offset=pin_pos)
-        if self.write_size is not None:
+        if self.write_size:
             for bit in range(self.num_wmasks):
                 en_pin = self.driver_insts[bit*self.write_size].get_pin("en")
                 # Determine width of wmask modified en_pin with/without col mux