mirror of https://github.com/VLSIDA/OpenRAM.git
Added option to output an extended configuration file that includes defaults.
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8bcbf005bf
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@ -93,6 +93,8 @@ class options(optparse.Values):
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trim_netlist = False
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trim_netlist = False
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# Run with extracted parasitics
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# Run with extracted parasitics
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use_pex = False
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use_pex = False
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# Output config with all options
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output_extended_config = False
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###################
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###################
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@ -63,6 +63,18 @@ class sram():
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def verilog_write(self, name):
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def verilog_write(self, name):
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self.s.verilog_write(name)
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self.s.verilog_write(name)
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def extended_config_write(self, name):
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"""Dump config file with all options.
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Include defaults and anything changed by input config."""
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f = open(name, "w")
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var_dict = dict((name, getattr(OPTS, name)) for name in dir(OPTS) if not name.startswith('__') and not callable(getattr(OPTS, name)))
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for var_name, var_value in var_dict.items():
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if isinstance(var_value, str):
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f.write(str(var_name) + " = " + "\"" + str(var_value) + "\"\n")
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else:
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f.write(str(var_name) + " = " + str(var_value)+ "\n")
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f.close()
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def save(self):
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def save(self):
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""" Save all the output files while reporting time to do it as well. """
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""" Save all the output files while reporting time to do it as well. """
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@ -137,3 +149,11 @@ class sram():
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debug.print_raw("Verilog: Writing to {0}".format(vname))
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debug.print_raw("Verilog: Writing to {0}".format(vname))
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self.verilog_write(vname)
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self.verilog_write(vname)
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print_time("Verilog", datetime.datetime.now(), start_time)
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print_time("Verilog", datetime.datetime.now(), start_time)
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# Write out options if specified
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if OPTS.output_extended_config:
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start_time = datetime.datetime.now()
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oname = OPTS.output_path + OPTS.output_name + "_extended.py"
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debug.print_raw("Extended Config: Writing to {0}".format(oname))
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self.extended_config_write(oname)
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print_time("Extended Config", datetime.datetime.now(), start_time)
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