mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-07 03:20:39 +02:00
Merge branch 'dev' into multibank
This commit is contained in:
Bugra Onal
@@ -28,6 +28,7 @@ class code_format_test(openram_test):
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continue
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errors += check_file_format_tab(code)
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errors += check_file_format_carriage(code)
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errors += check_file_format_whitespace(code)
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for code in source_codes:
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if re.search("gdsMill", code):
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@@ -51,7 +52,7 @@ def setup_files(path):
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files = []
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for (dir, _, current_files) in os.walk(path):
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for f in current_files:
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files.append(os.getenv("OPENRAM_HOME"))
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files.append(os.path.join(dir, f))
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nametest = re.compile("\.py$", re.IGNORECASE)
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select_files = list(filter(nametest.search, files))
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return select_files
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@@ -92,16 +93,43 @@ def check_file_format_carriage(file_name):
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if len(key_positions)>10:
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line_numbers = key_positions[:10] + [" ..."]
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else:
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line_numbers = key_positoins
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line_numbers = key_positions
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debug.info(0, '\nFound ' + str(len(key_positions)) + ' carriage returns in ' +
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str(file_name) + ' (lines ' + ",".join(str(x) for x in line_numbers) + ')')
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f.close()
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return len(key_positions)
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def check_file_format_whitespace(file_name):
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"""
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Check if file contains a line with whitespace at the end
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and return the number of these lines.
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"""
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f = open(file_name, "r")
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key_positions = []
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for num, line in enumerate(f.readlines()):
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if re.match(r".*[ \t]$", line):
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key_positions.append(num)
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if len(key_positions) > 0:
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if len(key_positions) > 10:
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line_numbers = key_positions[:10] + [" ..."]
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else:
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line_numbers = key_positions
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debug.info(0, "\nFound " + str(len(key_positions)) + " ending whitespace in " +
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str(file_name) + " (lines " + ",".join(str(x) for x in line_numbers) + ")")
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f.close()
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return len(key_positions)
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def check_print_output(file_name):
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"""Check if any files (except debug.py) call the _print_ function. We should
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use the debug output with verbosity instead!"""
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skip_files = ["printGDS.py", "uniquifyGDS.py", "processGDS.py", "model_data_util.py"]
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base_file_name = os.path.basename(file_name)
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if base_file_name in skip_files:
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return(0)
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file = open(file_name, "r+b")
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line = file.read().decode('utf-8')
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# skip comments with a hash
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@@ -43,7 +43,7 @@ class library_lvs_test(openram_test):
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self.assertEqual(drc_errors + lvs_errors, 0)
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globals.end_openram()
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def setup_files():
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gds_dir = OPTS.openram_tech + "/gds_lib"
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sp_dir = OPTS.openram_tech + "/lvs_lib"
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@@ -32,7 +32,7 @@ class replica_column_test(openram_test):
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debug.info(2, "Testing one right replica column for dual port")
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a = factory.create(module_type="replica_column", rows=4, rbl=[0, 1], replica_bit=5)
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self.local_check(a)
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debug.info(2, "Testing two (left, right) replica columns for dual port")
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a = factory.create(module_type="replica_column", rows=4, rbl=[1, 1], replica_bit=1)
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self.local_check(a)
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@@ -40,7 +40,7 @@ class replica_column_test(openram_test):
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debug.info(2, "Testing two (left, right) replica columns for dual port")
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a = factory.create(module_type="replica_column", rows=4, rbl=[1, 1], replica_bit=6)
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self.local_check(a)
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globals.end_openram()
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# run the test from the command line
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@@ -63,7 +63,7 @@ class port_data_spare_cols_test(openram_test):
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OPTS.num_r_ports = 1
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OPTS.num_w_ports = 1
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globals.setup_bitcell()
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c.num_words=16
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c.words_per_row=1
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factory.reset()
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@@ -31,7 +31,7 @@ class psingle_bank_test(openram_test):
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OPTS.num_w_ports = 0
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OPTS.num_r_ports = 0
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globals.setup_bitcell()
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c = sram_config(word_size=4,
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num_words=16)
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@@ -15,7 +15,7 @@ from globals import OPTS
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from sram_factory import factory
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import debug
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class psram_1bank_2mux_1rw_1w_test(openram_test):
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def runTest(self):
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@@ -28,7 +28,7 @@ class psram_1bank_2mux_1rw_1w_wmask_test(openram_test):
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OPTS.num_w_ports = 1
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OPTS.num_r_ports = 0
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globals.setup_bitcell()
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c = sram_config(word_size=8,
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write_size=4,
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num_words=32,
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@@ -22,7 +22,7 @@ class sram_1bank_4mux_1rw_1r_test(openram_test):
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config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
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globals.init_openram(config_file)
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from modules import sram_config
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OPTS.num_rw_ports = 1
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OPTS.num_r_ports = 1
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OPTS.num_w_ports = 0
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@@ -92,8 +92,8 @@ class model_delay_test(openram_test):
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else:
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self.assertTrue(False) # other techs fail
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print('spice_delays', spice_delays)
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print('model_delays', model_delays)
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debug.info(3, 'spice_delays {}'.fomrat(spice_delays))
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debug.info(3, 'model_delays {}'.format(model_delays))
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# Check if no too many or too few results
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self.assertTrue(len(spice_delays.keys())==len(model_delays.keys()))
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@@ -96,7 +96,7 @@ class timing_sram_test(openram_test):
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'slew_hl': [2.039655],
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'slew_lh': [2.039655],
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'write0_power': [19.31883],
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'write1_power': [15.297369999999999]}
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'write1_power': [15.297369999999999]}
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else:
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self.assertTrue(False) # other techs fail
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@@ -58,7 +58,7 @@ class regression_model_test(openram_test):
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debug.info(1, "Probe address {0} probe data bit {1}".format(probe_address, probe_data))
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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#m = linear_regression(s.s, tempspice, corner)
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m = neural_network(s.s, tempspice, corner)
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only_test = ['rise_delay']
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@@ -24,7 +24,7 @@ class psram_1bank_2mux_func_test(openram_test):
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OPTS.analytical_delay = False
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OPTS.netlist_only = True
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OPTS.trim_netlist = False
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OPTS.bitcell = "pbitcell"
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OPTS.replica_bitcell="replica_pbitcell"
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OPTS.dummy_bitcell="dummy_pbitcell"
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@@ -25,7 +25,7 @@ class psram_1bank_4mux_func_test(openram_test):
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OPTS.analytical_delay = False
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OPTS.netlist_only = True
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OPTS.trim_netlist = False
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OPTS.bitcell = "pbitcell"
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OPTS.replica_bitcell="replica_pbitcell"
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OPTS.dummy_bitcell="dummy_pbitcell"
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@@ -25,7 +25,7 @@ class psram_1bank_8mux_func_test(openram_test):
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OPTS.analytical_delay = False
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OPTS.netlist_only = True
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OPTS.trim_netlist = False
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OPTS.bitcell = "pbitcell"
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OPTS.replica_bitcell="replica_pbitcell"
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OPTS.dummy_bitcell="dummy_pbitcell"
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@@ -24,7 +24,7 @@ class psram_1bank_nomux_func_test(openram_test):
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OPTS.analytical_delay = False
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OPTS.netlist_only = True
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OPTS.trim_netlist = False
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OPTS.bitcell = "pbitcell"
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OPTS.replica_bitcell="replica_pbitcell"
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OPTS.dummy_bitcell="dummy_pbitcell"
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@@ -25,7 +25,7 @@ class sram_1bank_2mux_func_test(openram_test):
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OPTS.analytical_delay = False
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OPTS.netlist_only = True
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OPTS.trim_netlist = False
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# This is a hack to reload the characterizer __init__ with the spice version
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from importlib import reload
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import characterizer
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@@ -25,7 +25,7 @@ class sram_1bank_2mux_func_test(openram_test):
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OPTS.analytical_delay = False
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OPTS.netlist_only = True
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OPTS.trim_netlist = False
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# This is a hack to reload the characterizer __init__ with the spice version
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from importlib import reload
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import characterizer
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@@ -25,7 +25,7 @@ class sram_1bank_4mux_func_test(openram_test):
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OPTS.analytical_delay = False
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OPTS.netlist_only = True
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OPTS.trim_netlist = False
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# This is a hack to reload the characterizer __init__ with the spice version
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from importlib import reload
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import characterizer
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@@ -25,7 +25,7 @@ class sram_1bank_8mux_func_test(openram_test):
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OPTS.analytical_delay = False
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OPTS.netlist_only = True
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OPTS.trim_netlist = False
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# This is a hack to reload the characterizer __init__ with the spice version
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from importlib import reload
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import characterizer
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@@ -81,8 +81,8 @@ class ngspice_pex_pinv_test(openram_test):
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test_sim = self.write_simulation(sim_file, test_module, top_level_name)
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test_sim.run_sim("stim.sp")
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delay = parse_spice_list(log_file_name, "pinv_delay")
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os.chdir(cwd)
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os.chdir(cwd)
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return delay
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def write_simulation(self, sim_file, cir_file, top_module_name):
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@@ -78,7 +78,7 @@ class openram_back_end_test(openram_test):
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filename = "{0}{1}".format(out_path, out_file)
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debug.info(1, "Checking for file: " + filename)
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self.assertEqual(os.path.exists(filename), True)
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# Make sure there is any .lib file
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import glob
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files = glob.glob('{0}/*.lib'.format(out_path))
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@@ -55,9 +55,9 @@ def fork_tests(num_threads):
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results = []
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test_partitions = partition_unit_tests(suite, num_threads)
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suite._tests[:] = []
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def do_fork(suite):
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for test_partition in test_partitions:
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test_suite = unittest.TestSuite(test_partition)
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test_partition[:] = []
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@@ -103,9 +103,9 @@ if num_threads == 1:
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final_suite = suite
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else:
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final_suite = ConcurrentTestSuite(suite, fork_tests(num_threads))
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test_result = test_runner.run(final_suite)
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# import verify
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# verify.print_drc_stats()
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# verify.print_lvs_stats()
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