mirror of https://github.com/VLSIDA/OpenRAM.git
Do not extract bb (bounding box) layer in SCN4M_SUBM tech file
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e90ea4e737
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aeb9594877
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@ -333,7 +333,7 @@ style lambda=0.20(p)
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templayer TCSB nwsd,nwsc
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templayer TCSB nwsd,nwsc
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grow 40
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grow 40
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and-not TNWR
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and-not TNWR
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layer CSB nwsd,nwsc,nwr
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layer CSB nwsd,nwsc,nwr
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grow 140
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grow 140
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and-not TCSB
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and-not TCSB
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@ -375,7 +375,7 @@ style lambda=0.20(p)
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bloat-or pdiff,apres,rpd,pdc/a * 40 nsd,nsc/a 0
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bloat-or pdiff,apres,rpd,pdc/a * 40 nsd,nsc/a 0
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or TPS
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or TPS
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#final pselect
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#final pselect
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templayer FSP
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templayer FSP
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bloat-or pdiff,apres,rpd,pfet,psd,pdc/a,psc/a,pfet * 40 ndiff,anres,rnd,ndc/a,nsd,nsc/a,nfet 0
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bloat-or pdiff,apres,rpd,pfet,psd,pdc/a,psc/a,pfet * 40 ndiff,anres,rnd,ndc/a,nsd,nsc/a,nfet 0
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or XDP
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or XDP
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@ -772,7 +772,7 @@ style lambda=0.20(cp)
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templayer TCSB nwsd,nwsc
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templayer TCSB nwsd,nwsc
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grow 40
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grow 40
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and-not TNWR
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and-not TNWR
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layer CSB nwsd,nwsc,nwr
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layer CSB nwsd,nwsc,nwr
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grow 140
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grow 140
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and-not TCSB
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and-not TCSB
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@ -814,7 +814,7 @@ style lambda=0.20(cp)
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bloat-or pdiff,apres,rpd,pdc/a * 40 nsd,nsc/a 0
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bloat-or pdiff,apres,rpd,pdc/a * 40 nsd,nsc/a 0
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or TPS
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or TPS
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#final pselect
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#final pselect
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templayer FSP
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templayer FSP
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bloat-or pdiff,apres,rpd,pfet,psd,pdc/a,psc/a,pfet * 40 ndiff,anres,rnd,ndc/a,nsd,nsc/a,nfet 0
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bloat-or pdiff,apres,rpd,pfet,psd,pdc/a,psc/a,pfet * 40 ndiff,anres,rnd,ndc/a,nsd,nsc/a,nfet 0
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or XDP
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or XDP
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@ -1119,7 +1119,7 @@ style lambda=0.20(c)
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templayer TCSB nwsd,nwsc
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templayer TCSB nwsd,nwsc
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grow 40
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grow 40
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and-not TNWR
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and-not TNWR
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layer CSB nwsd,nwsc,nwr
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layer CSB nwsd,nwsc,nwr
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grow 140
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grow 140
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and-not TCSB
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and-not TCSB
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@ -1151,7 +1151,7 @@ style lambda=0.20(c)
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bloat-or pdiff,apres,rpd,pdc/a * 40 nsd,nsc/a 0
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bloat-or pdiff,apres,rpd,pdc/a * 40 nsd,nsc/a 0
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or TPS
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or TPS
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#final pselect
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#final pselect
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templayer FSP
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templayer FSP
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bloat-or pdiff,apres,rpd,pfet,psd,pdc/a,psc/a,pfet * 40 ndiff,anres,rnd,ndc/a,nsd,nsc/a,nfet 0
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bloat-or pdiff,apres,rpd,pfet,psd,pdc/a,psc/a,pfet * 40 ndiff,anres,rnd,ndc/a,nsd,nsc/a,nfet 0
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or XDP
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or XDP
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@ -1456,7 +1456,7 @@ style lambda=0.20()
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templayer TCSB nwsd,nwsc
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templayer TCSB nwsd,nwsc
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grow 40
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grow 40
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and-not TNWR
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and-not TNWR
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layer CSB nwsd,nwsc,nwr
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layer CSB nwsd,nwsc,nwr
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grow 140
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grow 140
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and-not TCSB
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and-not TCSB
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@ -1488,7 +1488,7 @@ style lambda=0.20()
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bloat-or pdiff,apres,rpd,pdc/a * 40 nsd,nsc/a 0
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bloat-or pdiff,apres,rpd,pdc/a * 40 nsd,nsc/a 0
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or TPS
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or TPS
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#final pselect
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#final pselect
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templayer FSP
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templayer FSP
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bloat-or pdiff,apres,rpd,pfet,psd,pdc/a,psc/a,pfet * 40 ndiff,anres,rnd,ndc/a,nsd,nsc/a,nfet 0
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bloat-or pdiff,apres,rpd,pfet,psd,pdc/a,psc/a,pfet * 40 ndiff,anres,rnd,ndc/a,nsd,nsc/a,nfet 0
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or XDP
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or XDP
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@ -6471,7 +6471,7 @@ end
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mzrouter
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mzrouter
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style irouter
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style irouter
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# layer hCost vCost jogCost hintCost
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# layer hCost vCost jogCost hintCost
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layer metal4 2 1 2 1
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layer metal4 2 1 2 1
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layer metal3 1 2 2 1
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layer metal3 1 2 2 1
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layer metal2 2 1 2 1
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layer metal2 2 1 2 1
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@ -6944,7 +6944,7 @@ drc
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"Silicide-Block overlap of Silicide-Block polyR/activeR < 2 (Mosis #20.15)"
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"Silicide-Block overlap of Silicide-Block polyR/activeR < 2 (Mosis #20.15)"
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edge4way sb,pres,anres,apres diff,ndiff,rnd,nfet,nsd,nwsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a 3 diff,ndiff,rnd,nfet,nsd,nwsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a 0 0 \
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edge4way sb,pres,anres,apres diff,ndiff,rnd,nfet,nsd,nwsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a 3 diff,ndiff,rnd,nfet,nsd,nwsd,pdiff,rpd,pfet,psd,ndc/a,nsc/a,nwsc/a,pdc/a,psc/a 0 0 \
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"Diffusion overhang of Silicide-Block < 3 (Mosis #20.17)
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"Diffusion overhang of Silicide-Block < 3 (Mosis #20.17)
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spacing gv3 gv3 3 touching_ok \
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spacing gv3 gv3 3 touching_ok \
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"GV3 via spacing < 3 (Mosis #21.2)"
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"GV3 via spacing < 3 (Mosis #21.2)"
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@ -7145,7 +7145,7 @@ drc
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spacing m4p m4p 4 touching_ok \
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spacing m4p m4p 4 touching_ok \
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"Metal4 PIN spacing < 4 (do_pins)"
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"Metal4 PIN spacing < 4 (do_pins)"
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#CC cifstyle lambda=0.20(p)
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#CC cifstyle lambda=0.20(p)
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#CC cifwidth CWN 240 \
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#CC cifwidth CWN 240 \
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#CC "generated CIF layer CWN width will be < 12 (';cif see CWN')"
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#CC "generated CIF layer CWN width will be < 12 (';cif see CWN')"
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#CC cifspacing CWN CWN 120 touching_ok \
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#CC cifspacing CWN CWN 120 touching_ok \
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@ -7223,6 +7223,7 @@ extract
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resist (m2,fm2,rm2,m2c,m3c,m3c)/metal2 70
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resist (m2,fm2,rm2,m2c,m3c,m3c)/metal2 70
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resist (m3,fm3,rm3,m3c,m4c,m4c)/metal3 80
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resist (m3,fm3,rm3,m3c,m4c,m4c)/metal3 80
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resist (m4,fm4,rm4,m4c,pad)/metal4 40
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resist (m4,fm4,rm4,m4c,pad)/metal4 40
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resist bb None
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contact ndc 4 4100
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contact ndc 4 4100
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contact pdc 4 3400
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contact pdc 4 3400
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@ -7288,25 +7289,25 @@ extract
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sideoverlap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~space/w 2.226 ~space/a
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sideoverlap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~space/w 2.226 ~space/a
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#rnw
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#rnw
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overlap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 rnw,nwr/active 1.666
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overlap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 rnw,nwr/active 1.666
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sideoverlap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 rnw,nwr/active 2.226
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sideoverlap (m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,pdc,pc,m2c)/metal1 rnw,nwr/active 2.226
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#metal1-diff blocked by
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#metal1-diff blocked by
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overlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 (ndiff,anres,rnd,ndc)/active 1.640
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overlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 (ndiff,anres,rnd,ndc)/active 1.640
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sideoverlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 (ndiff,anres,rnd,ndc)/active 2.226
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sideoverlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 (ndiff,anres,rnd,ndc)/active 2.226
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overlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 (pdiff,apres,rpd,pdc)/active 1.640
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overlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 (pdiff,apres,rpd,pdc)/active 1.640
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sideoverlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 (pdiff,apres,rpd,pdc)/active 2.226
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sideoverlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 (pdiff,apres,rpd,pdc)/active 2.226
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#metal1-poly blocked by
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#metal1-poly blocked by
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overlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 (poly,fp,pres,rp,pc,nfet,pfet,fet)/active 1.687
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overlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 (poly,fp,pres,rp,pc,nfet,pfet,fet)/active 1.687
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sideoverlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 (poly,fp,pres,rp,pc,nfet,pfet,fet)/active 2.250
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sideoverlap (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 ~(m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 (poly,fp,pres,rp,pc,nfet,pfet,fet)/active 2.250
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sideoverlap (poly,fp,pres,rp,pc,nfet,pfet,fet)/active ~(poly,fp,pres,rp,pc,nfet,pfet,fet)/active (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 2.250
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sideoverlap (poly,fp,pres,rp,pc,nfet,pfet,fet)/active ~(poly,fp,pres,rp,pc,nfet,pfet,fet)/active (m1,fm1,rm1,ndc,nsc,nwsc,pdc,psc,pc,m2c)/metal1 2.250
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#metal2
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#metal2
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sidewall (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (m2,fm2,rm2,m2c,m3c)/metal2 23.532
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sidewall (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 (m2,fm2,rm2,m2c,m3c)/metal2 23.532
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areacap (m2,fm2,rm2,m3c)/metal2 0.581
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areacap (m2,fm2,rm2,m3c)/metal2 0.581
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#metal2-sub blocked by
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#metal2-sub blocked by
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overlap (m2,fm2,rm2,m3c)/metal2 ~space/w 0.581 ~space/a,~space/m1
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overlap (m2,fm2,rm2,m3c)/metal2 ~space/w 0.581 ~space/a,~space/m1
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perimc (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 0.836
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perimc (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 0.836
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sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 ~space/w 0.836 ~space/a,~space/m1
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sideoverlap (m2,fm2,rm2,m2c,m3c)/metal2 ~(m2,fm2,rm2,m2c,m3c)/metal2 ~space/w 0.836 ~space/a,~space/m1
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@ -7732,4 +7733,3 @@ style gremlin
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pc/a,ndc/a,pdc/a,psc/a,nsc/a,nwsc/a,gc,gc,gc,gv1 X
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pc/a,ndc/a,pdc/a,psc/a,nsc/a,nwsc/a,gc,gc,gc,gv1 X
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end
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end
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