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Unit tests for pbitcell now passing, so commenting out skip line. Also gave pbitcell_array useful names in unit test for easier debugging

This commit is contained in:
Michael Timothy Grimes 2018-08-29 16:05:13 -07:00
parent 7ef7c084cd
commit aeaab13d28
2 changed files with 5 additions and 5 deletions
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2
compiler/tests/04_pbitcell_test.py
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@ -13,7 +13,7 @@ import debug
OPTS = globals.OPTS OPTS = globals.OPTS
@unittest.skip("SKIPPING 04_pbitcell_test") #@unittest.skip("SKIPPING 04_pbitcell_test")
class pbitcell_test(openram_test): class pbitcell_test(openram_test):
def runTest(self): def runTest(self):

8
compiler/tests/05_pbitcell_array_test.py
View File

@ -11,7 +11,7 @@ import globals
from globals import OPTS from globals import OPTS
import debug import debug
@unittest.skip("SKIPPING 05_pbitcell_array_test") #@unittest.skip("SKIPPING 05_pbitcell_array_test")
class pbitcell_array_test(openram_test): class pbitcell_array_test(openram_test):
def runTest(self): def runTest(self):
@ -26,7 +26,7 @@ class pbitcell_array_test(openram_test):
OPTS.rw_ports = 2 OPTS.rw_ports = 2
OPTS.r_ports = 2 OPTS.r_ports = 2
OPTS.w_ports = 2 OPTS.w_ports = 2
a = bitcell_array.bitcell_array(name="pbitcell_array", cols=4, rows=4) a = bitcell_array.bitcell_array(name="pbitcell_array_Rport_edge", cols=4, rows=4)
self.local_check(a) self.local_check(a)
debug.info(2, "Testing 4x4 array for multiport bitcell, with write ports at the edge of the bit cell") debug.info(2, "Testing 4x4 array for multiport bitcell, with write ports at the edge of the bit cell")
@ -34,7 +34,7 @@ class pbitcell_array_test(openram_test):
OPTS.rw_ports = 2 OPTS.rw_ports = 2
OPTS.r_ports = 0 OPTS.r_ports = 0
OPTS.w_ports = 2 OPTS.w_ports = 2
a = bitcell_array.bitcell_array(name="pbitcell_array", cols=4, rows=4) a = bitcell_array.bitcell_array(name="pbitcell_array_Wport_edge", cols=4, rows=4)
self.local_check(a) self.local_check(a)
debug.info(2, "Testing 4x4 array for multiport bitcell, with read/write ports at the edge of the bit cell") debug.info(2, "Testing 4x4 array for multiport bitcell, with read/write ports at the edge of the bit cell")
@ -42,7 +42,7 @@ class pbitcell_array_test(openram_test):
OPTS.rw_ports = 2 OPTS.rw_ports = 2
OPTS.r_ports = 0 OPTS.r_ports = 0
OPTS.w_ports = 0 OPTS.w_ports = 0
a = bitcell_array.bitcell_array(name="pbitcell_array", cols=4, rows=4) a = bitcell_array.bitcell_array(name="pbitcell_array_RWport_edge", cols=4, rows=4)
self.local_check(a) self.local_check(a)
globals.end_openram() globals.end_openram()