luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

add support for no rbl to port data

This commit is contained in:
Sam Crow 2023-04-05 15:33:45 -07:00
parent d00ba73bc9
commit ae6d271602
1 changed files with 12 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
compiler/modules/port_data.py
View File

@ -18,13 +18,14 @@ from openram import OPTS
class port_data(design):
"""
Create the data port (column mux, sense amps, write driver, etc.) for the given port number.
Port 0 always has the RBL on the left while port 1 is on the right.
When RBLs present: port 0 always has the RBL on the left while port 1 is on the right.
"""
def __init__(self, sram_config, port, num_spare_cols=None, bit_offsets=None, name="",):
def __init__(self, sram_config, port, has_rbl, num_spare_cols=None, bit_offsets=None, name="",):
sram_config.set_local_config(self)
self.port = port
self.has_rbl = has_rbl
if self.write_size != self.word_size:
self.num_wmasks = int(math.ceil(self.word_size / self.write_size))
else:
@ -115,6 +116,7 @@ class port_data(design):
def add_pins(self):
""" Adding pins for port data module"""
if self.has_rbl:
self.add_pin("rbl_bl", "INOUT")
self.add_pin("rbl_br", "INOUT")
for bit in range(self.num_cols):
@ -209,8 +211,9 @@ class port_data(design):
# Append an offset on the right
precharge_bit_offsets = self.bit_offsets + [self.bit_offsets[-1] + precharge_width]
# has_rbl is a boolean treated as 1 if true 0 if false typical python
self.precharge_array = factory.create(module_type="precharge_array",
columns=self.num_cols + self.num_spare_cols + 1,
columns=self.num_cols + self.num_spare_cols + self.has_rbl,
offsets=precharge_bit_offsets,
bitcell_bl=self.bl_names[self.port],
bitcell_br=self.br_names[self.port],
@ -294,7 +297,7 @@ class port_data(design):
mod=self.precharge_array)
temp = []
# Use left BLs for RBL
if self.port==0:
if self.port==0 and self.has_rbl:
temp.append("rbl_bl")
temp.append("rbl_br")
for bit in range(self.num_cols):
@ -306,7 +309,7 @@ class port_data(design):
temp.append("sparebr_{0}".format(bit))
# Use right BLs for RBL
if self.port==1:
if self.port==1 and self.has_rbl:
temp.append("rbl_bl")
temp.append("rbl_br")
temp.extend(["p_en_bar", "vdd"])
@ -683,11 +686,11 @@ class port_data(design):
""" Add the bitline pins for the given port """
# Connect one bitline to the RBL and offset the indices for the other BLs
if self.port==0:
if self.port==0 and self.has_rbl:
self.copy_layout_pin(self.precharge_array_inst, "bl_0", "rbl_bl")
self.copy_layout_pin(self.precharge_array_inst, "br_0", "rbl_br")
bit_offset=1
elif self.port==1:
elif self.port==1 and self.has_rbl:
self.copy_layout_pin(self.precharge_array_inst, "bl_{}".format(self.num_cols + self.num_spare_cols), "rbl_bl")
self.copy_layout_pin(self.precharge_array_inst, "br_{}".format(self.num_cols + self.num_spare_cols), "rbl_br")
bit_offset=0