mirror of https://github.com/VLSIDA/OpenRAM.git
Fix spice model bin parameter error
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@ -51,7 +51,7 @@ class pinv_dec(pinv.pinv):
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self.tx_mults = 1
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self.nmos_width = self.nmos_size * drc("minwidth_tx")
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self.pmos_width = self.pmos_size * drc("minwidth_tx")
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if self.bin_spice_models:
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if cell_props.ptx.bin_spice_models:
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self.nmos_width = self.nearest_bin("nmos", self.nmos_width)
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self.pmos_width = self.nearest_bin("pmos", self.pmos_width)
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@ -36,7 +36,7 @@ class pnor2(pgate.pgate):
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debug.check(size==1, "Size 1 pnor2 is only supported now.")
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self.tx_mults = 1
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if self.bin_spice_models:
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if cell_props.ptx.bin_spice_models:
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self.nmos_width = self.nearest_bin("nmos", self.nmos_width)
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self.pmos_width = self.nearest_bin("pmos", self.pmos_width)
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