mirror of https://github.com/VLSIDA/OpenRAM.git
use capped array to create banks
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@ -374,9 +374,12 @@ class bank(design):
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cols=cols,
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cols=cols,
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rows=self.num_rows)
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rows=self.num_rows)
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else:
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else:
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self.bitcell_array = factory.create(module_type="replica_bitcell_array",
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self.bitcell_array = factory.create(module_type="capped_replica_bitcell_array",
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cols=self.num_cols + self.num_spare_cols,
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cols=self.num_cols + self.num_spare_cols,
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rows=self.num_rows)
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rows=self.num_rows,
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rbl=[1, 1 if len(self.all_ports)>1 else 0],
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left_rbl=[0],
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right_rbl=[1] if len(self.all_ports)>1 else [])
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self.port_address = []
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self.port_address = []
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for port in self.all_ports:
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for port in self.all_ports:
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