mirror of https://github.com/VLSIDA/OpenRAM.git
Remove uniqe pbitcell id since it isn't needed. Convert dos EOL to unix EOL characters. Convert python2.7 to python3 in pbitcell.
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@ -15,11 +15,8 @@ class pbitcell(pgate.pgate):
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width = None
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height = None
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unique_id = 1
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def __init__(self, num_readwrite=OPTS.rw_ports, num_write=OPTS.w_ports, num_read=OPTS.r_ports):
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name = "pbitcell_{0}RW_{1}W_{2}R_{3}".format(num_readwrite, num_write, num_read, pbitcell.unique_id)
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pbitcell.unique_id += 1
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name = "pbitcell_{0}RW_{1}W_{2}R".format(num_readwrite, num_write, num_read)
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pgate.pgate.__init__(self, name)
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debug.info(2, "create a multi-port bitcell with {0} write ports and {1} read ports".format(num_write, num_read))
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@ -1,6 +1,6 @@
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#!/usr/bin/env python2.7
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#!/usr/bin/env python3
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"""
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Run a regresion test on a basic array
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Run a regression test on a basic array
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"""
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import unittest
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