mirror of https://github.com/VLSIDA/OpenRAM.git
Separate route conditions for s8
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@ -11,7 +11,6 @@ import math
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from sram_factory import factory
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from sram_factory import factory
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from vector import vector
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from vector import vector
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from globals import OPTS
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from globals import OPTS
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from errors import drc_error
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class hierarchical_decoder(design.design):
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class hierarchical_decoder(design.design):
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@ -234,19 +234,18 @@ class hierarchical_predecode(design.design):
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in_pin = "in_{}".format(inv_num)
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in_pin = "in_{}".format(inv_num)
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inv_out_pin = self.inv_inst[inv_num].get_pin("Z")
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inv_out_pin = self.inv_inst[inv_num].get_pin("Z")
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inv_out_pos = inv_out_pin.lr()
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# add output so that it is just below the vdd or gnd rail
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# add output so that it is just below the vdd or gnd rail
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# since this is where the p/n devices are and there are no
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# since this is where the p/n devices are and there are no
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# pins in the and gates.
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# pins in the and gates.
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if False and OPTS.tech_name == "sky130":
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if OPTS.tech_name == "sky130":
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rail_pos = vector(self.decode_rails[out_pin].cx(), inv_out_pos.y)
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inv_out_pos = inv_out_pin.lr()
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self.add_path(self.output_layer, [inv_out_pos, rail_pos])
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else:
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else:
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y_offset = (inv_num + 1) * self.inv.height - self.output_layer_pitch
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inv_out_pos = inv_out_pin.rc()
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right_pos = inv_out_pos + vector(self.inv.width - self.inv.get_pin("Z").rx(), 0)
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y_offset = (inv_num + 1) * self.inv.height - self.output_layer_pitch
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rail_pos = vector(self.decode_rails[out_pin].cx(), y_offset)
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right_pos = inv_out_pos + vector(self.inv.width - self.inv.get_pin("Z").rx(), 0)
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self.add_path(self.output_layer, [inv_out_pos, right_pos, vector(right_pos.x, y_offset), rail_pos])
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rail_pos = vector(self.decode_rails[out_pin].cx(), y_offset)
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self.add_path(self.output_layer, [inv_out_pos, right_pos, vector(right_pos.x, y_offset), rail_pos])
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self.add_via_stack_center(from_layer=inv_out_pin.layer,
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self.add_via_stack_center(from_layer=inv_out_pin.layer,
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to_layer=self.output_layer,
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to_layer=self.output_layer,
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