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OpenRAM
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fixed html typos, added logo, added placeholder timing and current, began ports section

This commit is contained in:
Jesse Cirimelli-Low 2018-10-17 19:27:09 -07:00
parent 5d6944953b
commit ab6afb7ca8
5 changed files with 63 additions and 20 deletions
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19
compiler/characterizer/lib.py
View File

@ -526,15 +526,15 @@ class lib:
for (corner, lib_name) in zip(self.corners, self.lib_files):
ports = ""
if OPTS.num_rw_ports>0:
ports += "{}_".format(OPTS.num_rw_ports)
if OPTS.num_w_ports>0:
ports += "{}_".format(OPTS.num_w_ports)
if OPTS.num_r_ports>0:
ports += "{}_".format(OPTS.num_r_ports)
# ports = ""
# if OPTS.num_rw_ports>0:
# ports += "{}_".format(OPTS.num_rw_ports)
# if OPTS.num_w_ports>0:
# ports += "{}_".format(OPTS.num_w_ports)
# if OPTS.num_r_ports>0:
# ports += "{}_".format(OPTS.num_r_ports)
datasheet.write("{0},{1},{2},{3},{4},{5},{6},{7},{8},{9},{10},{11},{12}".format("sram_{0}_{1}_{2}{3}".format(OPTS.word_size, OPTS.num_words, ports, OPTS.tech_name),
datasheet.write("{0},{1},{2},{3},{4},{5},{6},{7},{8},{9},{10},{11},{12},{13}".format("sram_{0}_{1}_{2}".format(OPTS.word_size, OPTS.num_words, OPTS.tech_name),
OPTS.num_words,
OPTS.num_banks,
OPTS.num_rw_ports,
@ -546,7 +546,8 @@ class lib:
self.corner[0],
round_time(self.char_sram_results["min_period"]),
self.out_dir,
lib_name))
lib_name,
OPTS.word_size))
datasheet.close()

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compiler/datasheet/assets/vlsi_logo.png Normal file
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20
compiler/datasheet/datasheet.py
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@ -3,10 +3,14 @@ from operating_conditions import *
from characterization_corners import *
from deliverables import *
from timing_and_current_data import *
from in_out import *
import os
from globals import OPTS
class datasheet():
def __init__(self,identifier):
self.io = []
self.corners = []
self.timing = []
self.operating = []
@ -14,6 +18,7 @@ class datasheet():
self.name = identifier
self.html = ""
def generate_html(self):
self.html = """<style>
#data {
@ -40,16 +45,25 @@ class datasheet():
color: white;
}
</style>"""
self.html +='<p style=font-size: 20px;font-family: "Trebuchet MS", Arial, Helvetica, sans-serif;>{0}</p>'
self.html +='<p style=font-size: 20px;font-family: "Trebuchet MS", Arial, Helvetica, sans-serif;>{0}</p>'
self.html +='<p style=font-size: 20px;font-family: "Trebuchet MS", Arial, Helvetica, sans-serif;>{0}</p>'
self.html +='<p style=font-size: 20px;font-family: "Trebuchet MS", Arial, Helvetica, sans-serif;>'+ self.name + '.html' + '</p>'
# self.html +='<p style=font-size: 20px;font-family: "Trebuchet MS", Arial, Helvetica, sans-serif;>{0}</p>'
# self.html +='<p style=font-size: 20px;font-family: "Trebuchet MS", Arial, Helvetica, sans-serif;>{0}</p>'
self.html +='<p style=font-size: 20px;font-family: "Trebuchet MS", Arial, Helvetica, sans-serif;>Ports and Configuration (DEBUG)</p>'
self.html += in_out(self.io,table_id='data').__html__().replace('&lt;','<').replace('&#34;','"').replace('&gt;',">")
self.html +='<p style=font-size: 20px;font-family: "Trebuchet MS", Arial, Helvetica, sans-serif;>Operating Conditions</p>'
self.html += operating_conditions(self.operating,table_id='data').__html__()
self.html += '<p style=font-size: 20px;font-family: "Trebuchet MS", Arial, Helvetica, sans-serif;>Timing and Current Data</p>'
self.html += timing_and_current_data(self.timing,table_id='data').__html__()
self.html += '<p style=font-size: 20px;font-family: "Trebuchet MS", Arial, Helvetica, sans-serif;>Characterization Corners</p>'
self.html += characterization_corners(self.corners,table_id='data').__html__()
self.html +='<p style=font-size: 20px;font-family: "Trebuchet MS", Arial, Helvetica, sans-serif;>Deliverables</p>'
self.html += deliverables(self.dlv,table_id='data').__html__().replace('&lt;','<').replace('&#34;','"').replace('&gt;',">")
self.html +='<p style=font-size: 20px;font-family: "Trebuchet MS", Arial, Helvetica, sans-serif;>*Feature only supported with characterizer</p>'
self.html +='<img src=' + os.path.abspath(os.environ.get("OPENRAM_HOME")) + '/datasheet/assets/vlsi_logo.png alt="VLSIDA" />'

31
compiler/datasheet/datasheet_gen.py
View File

@ -19,6 +19,7 @@ from operating_conditions import *
from timing_and_current_data import *
from characterization_corners import *
from datasheet import *
from in_out import *
def process_name(corner):
if corner == "TT":
@ -43,12 +44,13 @@ def parse_file(f,pages):
NUM_W_PORTS = row[4]
NUM_R_PORTS = row[5]
TECH_NAME = row[6]
TEMP = row[7]
VOLT = row[8]
TEMP = row[8]
VOLT = row[7]
PROC = row[9]
MIN_PERIOD = row[10]
OUT_DIR = row[11]
LIB_NAME = row[12]
WORD_SIZE = row[13]
for sheet in pages:
@ -95,21 +97,36 @@ def parse_file(f,pages):
new_sheet.operating.append(operating_conditions_item('Power supply (VDD) range',VOLT,VOLT,VOLT,'Volts'))
new_sheet.operating.append(operating_conditions_item('Operating Temperature',TEMP,TEMP,TEMP,'Celsius'))
try:
new_sheet.operating.append(operating_conditions_item('Operating Frequency (F)','','',str(math.floor(1000/float(MIN_PERIOD))),'MHz'))
new_sheet.operating.append(operating_conditions_item('Operating Frequency (F)*','','',str(math.floor(1000/float(MIN_PERIOD))),'MHz'))
except Exception:
new_sheet.operating.append(operating_conditions_item('Operating Frequency (F)','','',"unknown",'MHz')) #analytical model fails to provide MIN_PERIOD
new_sheet.operating.append(operating_conditions_item('Operating Frequency (F)*','','',"unknown",'MHz')) #analytical model fails to provide MIN_PERIOD
new_sheet.timing.append(timing_and_current_data_item('Cycle time','2','3','4'))
new_sheet.timing.append(timing_and_current_data_item('Access time','2','3','4'))
new_sheet.timing.append(timing_and_current_data_item('Positive clk setup','2','3','4'))
new_sheet.timing.append(timing_and_current_data_item('Positive clk hold','2','3','4'))
new_sheet.timing.append(timing_and_current_data_item('RW setup','2','3','4'))
new_sheet.timing.append(timing_and_current_data_item('RW hold','2','3','4'))
new_sheet.timing.append(timing_and_current_data_item('AC current','2','3','4'))
new_sheet.timing.append(timing_and_current_data_item('Standby current','2','3','4'))
new_sheet.timing.append(timing_and_current_data_item('Area','2','3','4'))
new_sheet.timing.append(timing_and_current_data_item('1','2','3','4'))
new_sheet.dlv.append(deliverables_item('.sp','SPICE netlists','<a href="file://{0}{1}.{2}">{1}.{2}</a>'.format(OUT_DIR,NAME,'sp')))
new_sheet.dlv.append(deliverables_item('.v','Verilog simulation models','<a href="file://{0}{1}.{2}">{1}.{2}</a>'.format(OUT_DIR,NAME,'v')))
new_sheet.dlv.append(deliverables_item('.gds','GDSII layout views','<a href="file://{0}{1}.{2}">{1}.{2}</a>'.format(OUT_DIR,NAME,'gds')))
new_sheet.dlv.append(deliverables_item('.lef','LEF files','<a href="file://{0}{1}.{2}">{1}.{2}</a>'.format(OUT_DIR,NAME,'lef')))
new_sheet.dlv.append(deliverables_item('.lib','Synthesis models','<a href="file://{0}">{1}</a>'.format(LIB_NAME,LIB_NAME.replace(OUT_DIR,''))))
new_sheet.io.append(in_out_item('WORD_SIZE',WORD_SIZE))
new_sheet.io.append(in_out_item('NUM_WORDS',NUM_WORDS))
new_sheet.io.append(in_out_item('NUM_BANKS',NUM_BANKS))
new_sheet.io.append(in_out_item('NUM_RW_PORTS',NUM_RW_PORTS))
new_sheet.io.append(in_out_item('NUM_R_PORTS',NUM_R_PORTS))
new_sheet.io.append(in_out_item('NUM_W_PORTS',NUM_W_PORTS))
class datasheet_gen():

11
compiler/datasheet/in_out.py Normal file
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@ -0,0 +1,11 @@
from flask_table import *
class in_out(Table):
typ = Col('Type')
description = Col('Description')
class in_out_item(object):
def __init__(self, typ, description):
self.typ = typ
self.description = description