mirror of https://github.com/VLSIDA/OpenRAM.git
Merge branch 'dev' into add_wmask
This commit is contained in:
jsowash
commit
ab27c70279
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@ -0,0 +1,135 @@
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#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California
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# All rights reserved.
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#
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"""
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Run regression tests/pex test on an extracted pinv to ensure pex functionality
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with HSPICE.
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"""
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import unittest
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from testutils import header,openram_test
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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import debug
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class hspice_pex_pinv_test(openram_test):
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def runTest(self):
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globals.init_openram("config_{0}".format(OPTS.tech_name))
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import pinv
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# load the hspice
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OPTS.spice_name="hspice"
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OPTS.analytical_delay = False
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# This is a hack to reload the characterizer __init__ with the spice version
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from importlib import reload
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import characterizer
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reload(characterizer)
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# generate the pinv
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prev_purge_value = OPTS.purge_temp
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OPTS.purge_temp = False # force set purge to false to save the sp file
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debug.info(2, "Checking 1x size inverter")
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tx = pinv.pinv(name="pinv", size=1)
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tempgds = "{0}{1}.gds".format(OPTS.openram_temp,tx.name)
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tx.gds_write(tempgds)
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tempsp = "{0}{1}.sp".format(OPTS.openram_temp,tx.name)
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tx.sp_write(tempsp)
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# make sure that the library simulation is successful\
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sp_delay = self.simulate_delay(test_module = tempsp,
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top_level_name = tx.name)
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if sp_delay is "Failed":
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self.fail('Library Spice module did not behave as expected')
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# now generate its pex file
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pex_file = self.run_pex(tx)
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OPTS.purge_temp = prev_purge_value # restore the old purge value
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# generate simulation for pex, make sure the simulation is successful
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pex_delay = self.simulate_delay(test_module = pex_file,
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top_level_name = tx.name)
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# make sure the extracted spice simulated
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if pex_delay is "Failed":
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self.fail('Pex file did not behave as expected')
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# if pex data is bigger than original spice file then result is ok
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# However this may not always be true depending on the netlist provided
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# comment out for now
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#debug.info(2,"pex_delay: {0}".format(pex_delay))
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#debug.info(2,"sp_delay: {0}".format(sp_delay))
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#assert pex_delay > sp_delay, "pex delay {0} is smaller than sp_delay {1}"\
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#.format(pex_delay,sp_delay)
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globals.end_openram()
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def simulate_delay(self, test_module, top_level_name):
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from characterizer import charutils
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from charutils import parse_spice_list
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# setup simulation
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sim_file = OPTS.openram_temp + "stim.sp"
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log_file_name = "timing"
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test_sim = self.write_simulation(sim_file, test_module, top_level_name)
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test_sim.run_sim()
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delay = parse_spice_list(log_file_name, "pinv_delay")
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return delay
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def write_simulation(self, sim_file, cir_file, top_module_name):
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""" write pex spice simulation for a pinv test"""
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import tech
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from characterizer import measurements, stimuli
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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sim_file = open(sim_file, "w")
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simulation = stimuli(sim_file,corner)
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# library files
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simulation.write_include(cir_file)
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# supply voltages
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simulation.gen_constant(sig_name ="vdd",
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v_val = tech.spice["nom_supply_voltage"])
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simulation.gen_constant(sig_name = "gnd",
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v_val = "0v")
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run_time = tech.spice["feasible_period"] * 4
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# input voltage
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clk_period = tech.spice["feasible_period"]
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simulation.gen_pwl(sig_name ="input",
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clk_times = [clk_period,clk_period],
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data_values = [1,0],
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period = clk_period,
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slew = 0.001*tech.spice["feasible_period"],
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setup = 0)
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# instantiation of simulated pinv
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simulation.inst_model(pins = ["input", "output", "vdd", "gnd"],
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model_name = top_module_name)
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# delay measurement
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delay_measure = measurements.delay_measure(measure_name = "pinv_delay",
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trig_name = "input",
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targ_name = "output",
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trig_dir_str = "FALL",
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targ_dir_str = "RISE",
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has_port = False)
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trig_td = trag_td = 0.01 * run_time
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rest_info = trig_td,trag_td,tech.spice["nom_supply_voltage"]
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delay_measure.write_measure(simulation, rest_info)
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simulation.write_control(end_time = run_time)
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sim_file.close()
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return simulation
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# run the test from the command line
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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|
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@ -0,0 +1,137 @@
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#!/usr/bin/env python3
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# See LICENSE for licensing information.
|
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#
|
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# Copyright (c) 2016-2019 Regents of the University of California
|
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# All rights reserved.
|
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#
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"""
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Run regression tests/pex test on an extracted pinv to ensure pex functionality
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with Ngspice.
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"""
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import unittest
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from testutils import header,openram_test
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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import debug
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class ngspice_pex_pinv_test(openram_test):
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def runTest(self):
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globals.init_openram("config_{0}".format(OPTS.tech_name))
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import pinv
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# load the ngspice
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OPTS.spice_name="ngspice"
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OPTS.analytical_delay = False
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# This is a hack to reload the characterizer __init__ with the spice version
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from importlib import reload
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import characterizer
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reload(characterizer)
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# generate the pinv module
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prev_purge_value = OPTS.purge_temp
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OPTS.purge_temp = False # force set purge to false to save the sp file
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debug.info(2, "Checking 1x size inverter")
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tx = pinv.pinv(name="pinv", size=1)
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tempgds = "{0}{1}.gds".format(OPTS.openram_temp,tx.name)
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tx.gds_write(tempgds)
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tempsp = "{0}{1}.sp".format(OPTS.openram_temp,tx.name)
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tx.sp_write(tempsp)
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# make sure that the library simulation is successful
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sp_delay = self.simulate_delay(test_module = tempsp,
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top_level_name = tx.name)
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if sp_delay is "Failed":
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self.fail('Library Spice module did not behave as expected')
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# now generate its pex file
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pex_file = self.run_pex(tx)
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OPTS.purge_temp = prev_purge_value # restore the old purge value
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# generate simulation for pex, make sure the simulation is successful
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pex_delay = self.simulate_delay(test_module = pex_file,
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top_level_name = tx.name)
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# make sure the extracted spice simulated
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if pex_delay is "Failed":
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self.fail('Pex file did not behave as expected')
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# if pex data is bigger than original spice file then result is ok
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# However this may not always be true depending on the netlist provided
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# comment out for now
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#debug.info(2,"pex_delay: {0}".format(pex_delay))
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#debug.info(2,"sp_delay: {0}".format(sp_delay))
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#assert pex_delay > sp_delay, "pex delay {0} is smaller than sp_delay {1}"\
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#.format(pex_delay,sp_delay)
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globals.end_openram()
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def simulate_delay(self, test_module, top_level_name):
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from characterizer import charutils
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from charutils import parse_spice_list
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# setup simulation
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sim_file = OPTS.openram_temp + "stim.sp"
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log_file_name = "timing"
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test_sim = self.write_simulation(sim_file, test_module, top_level_name)
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test_sim.run_sim()
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delay = parse_spice_list(log_file_name, "pinv_delay")
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return delay
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def write_simulation(self, sim_file, cir_file, top_module_name):
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""" write pex spice simulation for a pinv test"""
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import tech
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from characterizer import measurements, stimuli
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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sim_file = open(sim_file, "w")
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simulation = stimuli(sim_file,corner)
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# library files
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simulation.write_include(cir_file)
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# supply voltages
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simulation.gen_constant(sig_name ="vdd",
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v_val = tech.spice["nom_supply_voltage"])
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# The scn4m_subm and ngspice combination will have a gnd source error:
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# "Fatal error: instance vgnd is a shorted VSRC"
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# However, remove gnd power for all techa pass for this test
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# simulation.gen_constant(sig_name = "gnd",
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# v_val = "0v")
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run_time = tech.spice["feasible_period"] * 4
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# input voltage
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clk_period = tech.spice["feasible_period"]
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simulation.gen_pwl(sig_name ="input",
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clk_times = [clk_period,clk_period],
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data_values = [1,0],
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period = clk_period,
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slew = 0.001*tech.spice["feasible_period"],
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setup = 0)
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# instantiation of simulated pinv
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simulation.inst_model(pins = ["input", "output", "vdd", "gnd"],
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model_name = top_module_name)
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# delay measurement
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delay_measure = measurements.delay_measure(measure_name = "pinv_delay",
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trig_name = "input",
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targ_name = "output",
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trig_dir_str = "FALL",
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targ_dir_str = "RISE",
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has_port = False)
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trig_td = trag_td = 0.01 * run_time
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rest_info = trig_td,trag_td,tech.spice["nom_supply_voltage"]
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delay_measure.write_measure(simulation, rest_info)
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simulation.write_control(end_time = run_time)
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sim_file.close()
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return simulation
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|
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# run the test from the command line
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
|
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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@ -63,6 +63,17 @@ class openram_test(unittest.TestCase):
|
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if OPTS.purge_temp:
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self.cleanup()
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def run_pex(self, a, output=None):
|
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if output == None:
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output = OPTS.openram_temp + a.name + ".pex.netlist"
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tempspice = "{0}{1}.sp".format(OPTS.openram_temp,a.name)
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tempgds = "{0}{1}.gds".format(OPTS.openram_temp,a.name)
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|
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import verify
|
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result=verify.run_pex(a.name, tempgds, tempspice, output=output, final_verification=False)
|
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if result != 0:
|
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self.fail("PEX ERROR: {}".format(a.name))
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return output
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|
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def find_feasible_test_period(self, delay_obj, sram, load, slew):
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"""Creates a delay simulation to determine a feasible period for the functional tests to run.
|
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|
|
@ -298,16 +309,18 @@ def header(filename, technology):
|
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|
||||
def debugTestRunner(post_mortem=None):
|
||||
"""unittest runner doing post mortem debugging on failing tests"""
|
||||
if post_mortem is None:
|
||||
if post_mortem is None and not OPTS.purge_temp:
|
||||
post_mortem = pdb.post_mortem
|
||||
class DebugTestResult(unittest.TextTestResult):
|
||||
def addError(self, test, err):
|
||||
# called before tearDown()
|
||||
traceback.print_exception(*err)
|
||||
if post_mortem:
|
||||
post_mortem(err[2])
|
||||
super(DebugTestResult, self).addError(test, err)
|
||||
def addFailure(self, test, err):
|
||||
traceback.print_exception(*err)
|
||||
if post_mortem:
|
||||
post_mortem(err[2])
|
||||
super(DebugTestResult, self).addFailure(test, err)
|
||||
return unittest.TextTestRunner(resultclass=DebugTestResult)
|
||||
|
|
|
|||
|
|
@ -138,9 +138,12 @@ def write_calibre_pex_script(cell_name, extract, output, final_verification):
|
|||
# check if lvs report has been done
|
||||
# if not run drc and lvs
|
||||
if not os.path.isfile(cell_name + ".lvs.report"):
|
||||
gds_name = OPTS.openram_temp +"/"+ cell_name + ".gds"
|
||||
sp_name = OPTS.openram_temp +"/"+ cell_name + ".sp"
|
||||
run_drc(cell_name, gds_name)
|
||||
run_lvs(cell_name, gds_name, sp_name)
|
||||
|
||||
from tech import drc
|
||||
pex_rules = drc["xrc_rules"]
|
||||
pex_runset = {
|
||||
'pexRulesFile': pex_rules,
|
||||
|
|
@ -317,7 +320,7 @@ def run_pex(cell_name, gds_name, sp_name, output=None, final_verification=False)
|
|||
global num_pex_runs
|
||||
num_pex_runs += 1
|
||||
|
||||
write_calibre_pex_script()
|
||||
write_calibre_pex_script(cell_name,True,output,final_verification)
|
||||
|
||||
(outfile, errfile, resultsfile) = run_script(cell_name, "pex")
|
||||
|
||||
|
|
|
|||
|
|
@ -257,9 +257,9 @@ def run_pex(name, gds_name, sp_name, output=None, final_verification=False):
|
|||
|
||||
global num_pex_runs
|
||||
num_pex_runs += 1
|
||||
|
||||
debug.warning("PEX using magic not implemented.")
|
||||
return 1
|
||||
#debug.warning("PEX using magic not implemented.")
|
||||
#return 1
|
||||
os.chdir(OPTS.openram_temp)
|
||||
|
||||
from tech import drc
|
||||
if output == None:
|
||||
|
|
@ -271,7 +271,50 @@ def run_pex(name, gds_name, sp_name, output=None, final_verification=False):
|
|||
run_drc(name, gds_name)
|
||||
run_lvs(name, gds_name, sp_name)
|
||||
|
||||
# pex_fix did run the pex using a script while dev orignial method
|
||||
# use batch mode.
|
||||
# the dev old code using batch mode does not run and is split into functions
|
||||
#pex_runset = write_batch_pex_rule(gds_name,name,sp_name,output)
|
||||
pex_runset = write_script_pex_rule(gds_name,name,output)
|
||||
|
||||
errfile = "{0}{1}.pex.err".format(OPTS.openram_temp, name)
|
||||
outfile = "{0}{1}.pex.out".format(OPTS.openram_temp, name)
|
||||
|
||||
# bash mode command from dev branch
|
||||
#batch_cmd = "{0} -gui -pex {1}pex_runset -batch 2> {2} 1> {3}".format(OPTS.pex_exe,
|
||||
# OPTS.openram_temp,
|
||||
# errfile,
|
||||
# outfile)
|
||||
script_cmd = "{0} 2> {1} 1> {2}".format(pex_runset,
|
||||
errfile,
|
||||
outfile)
|
||||
cmd = script_cmd
|
||||
debug.info(2, cmd)
|
||||
os.system(cmd)
|
||||
|
||||
# rename technology models
|
||||
pex_nelist = open(output, 'r')
|
||||
s = pex_nelist.read()
|
||||
pex_nelist.close()
|
||||
s = s.replace('pfet','p')
|
||||
s = s.replace('nfet','n')
|
||||
f = open(output, 'w')
|
||||
f.write(s)
|
||||
f.close()
|
||||
|
||||
# also check the output file
|
||||
f = open(outfile, "r")
|
||||
results = f.readlines()
|
||||
f.close()
|
||||
out_errors = find_error(results)
|
||||
debug.check(os.path.isfile(output),"Couldn't find PEX extracted output.")
|
||||
|
||||
correct_port(name,output,sp_name)
|
||||
return out_errors
|
||||
|
||||
def write_batch_pex_rule(gds_name,name,sp_name,output):
|
||||
"""
|
||||
The dev branch old batch mode runset
|
||||
2. magic can perform extraction with the following:
|
||||
#!/bin/sh
|
||||
rm -f $1.ext
|
||||
|
|
@ -289,7 +332,6 @@ def run_pex(name, gds_name, sp_name, output=None, final_verification=False):
|
|||
quit -noprompt
|
||||
EOF
|
||||
"""
|
||||
|
||||
pex_rules = drc["xrc_rules"]
|
||||
pex_runset = {
|
||||
'pexRulesFile': pex_rules,
|
||||
|
|
@ -307,42 +349,89 @@ def run_pex(name, gds_name, sp_name, output=None, final_verification=False):
|
|||
}
|
||||
|
||||
# write the runset file
|
||||
f = open(OPTS.openram_temp + "pex_runset", "w")
|
||||
for k in sorted(pex_runset.iterkeys()):
|
||||
file = OPTS.openram_temp + "pex_runset"
|
||||
f = open(file, "w")
|
||||
for k in sorted(pex_runset.keys()):
|
||||
f.write("*{0}: {1}\n".format(k, pex_runset[k]))
|
||||
f.close()
|
||||
return file
|
||||
|
||||
# run pex
|
||||
cwd = os.getcwd()
|
||||
os.chdir(OPTS.openram_temp)
|
||||
errfile = "{0}{1}.pex.err".format(OPTS.openram_temp, name)
|
||||
outfile = "{0}{1}.pex.out".format(OPTS.openram_temp, name)
|
||||
def write_script_pex_rule(gds_name,cell_name,output):
|
||||
global OPTS
|
||||
run_file = OPTS.openram_temp + "run_pex.sh"
|
||||
f = open(run_file, "w")
|
||||
f.write("#!/bin/sh\n")
|
||||
f.write("{} -dnull -noconsole << eof\n".format(OPTS.drc_exe[1]))
|
||||
f.write("gds polygon subcell true\n")
|
||||
f.write("gds warning default\n")
|
||||
f.write("gds read {}\n".format(gds_name))
|
||||
f.write("load {}\n".format(cell_name))
|
||||
f.write("select top cell\n")
|
||||
f.write("expand\n")
|
||||
f.write("port makeall\n")
|
||||
extract = True
|
||||
if not extract:
|
||||
pre = "#"
|
||||
else:
|
||||
pre = ""
|
||||
f.write(pre+"extract\n".format(cell_name))
|
||||
#f.write(pre+"ext2spice hierarchy on\n")
|
||||
#f.write(pre+"ext2spice format ngspice\n")
|
||||
#f.write(pre+"ext2spice renumber off\n")
|
||||
#f.write(pre+"ext2spice scale off\n")
|
||||
#f.write(pre+"ext2spice blackbox on\n")
|
||||
f.write(pre+"ext2spice subcircuit top on\n")
|
||||
#f.write(pre+"ext2spice global off\n")
|
||||
f.write(pre+"ext2spice {}\n".format(cell_name))
|
||||
f.write("quit -noprompt\n")
|
||||
f.write("eof\n")
|
||||
f.write("mv {0}.spice {1}\n".format(cell_name,output))
|
||||
|
||||
cmd = "{0} -gui -pex {1}pex_runset -batch 2> {2} 1> {3}".format(OPTS.pex_exe,
|
||||
OPTS.openram_temp,
|
||||
errfile,
|
||||
outfile)
|
||||
debug.info(2, cmd)
|
||||
os.system(cmd)
|
||||
os.chdir(cwd)
|
||||
|
||||
# also check the output file
|
||||
f = open(outfile, "r")
|
||||
results = f.readlines()
|
||||
f.close()
|
||||
os.system("chmod u+x {}".format(run_file))
|
||||
return run_file
|
||||
|
||||
def find_error(results):
|
||||
# Errors begin with "ERROR:"
|
||||
test = re.compile("ERROR:")
|
||||
stdouterrors = list(filter(test.search, results))
|
||||
for e in stdouterrors:
|
||||
debug.error(e.strip("\n"))
|
||||
|
||||
out_errors = len(stdouterrors)
|
||||
|
||||
debug.check(os.path.isfile(output),"Couldn't find PEX extracted output.")
|
||||
|
||||
return out_errors
|
||||
|
||||
def correct_port(name, output_file_name, ref_file_name):
|
||||
pex_file = open(output_file_name, "r")
|
||||
contents = pex_file.read()
|
||||
# locate the start of circuit definition line
|
||||
match = re.search(".subckt " + str(name) + ".*", contents)
|
||||
match_index_start = match.start()
|
||||
pex_file.seek(match_index_start)
|
||||
rest_text = pex_file.read()
|
||||
# locate the end of circuit definition line
|
||||
match = re.search(r'\n', rest_text)
|
||||
match_index_end = match.start()
|
||||
# store the unchanged part of pex file in memory
|
||||
pex_file.seek(0)
|
||||
part1 = pex_file.read(match_index_start)
|
||||
pex_file.seek(match_index_start + match_index_end)
|
||||
part2 = pex_file.read()
|
||||
pex_file.close()
|
||||
|
||||
# obtain the correct definition line from the original spice file
|
||||
sp_file = open(ref_file_name, "r")
|
||||
contents = sp_file.read()
|
||||
circuit_title = re.search(".SUBCKT " + str(name) + ".*\n", contents)
|
||||
circuit_title = circuit_title.group()
|
||||
sp_file.close()
|
||||
|
||||
# write the new pex file with info in the memory
|
||||
output_file = open(output_file_name, "w")
|
||||
output_file.write(part1)
|
||||
output_file.write(circuit_title)
|
||||
output_file.write(part2)
|
||||
output_file.close()
|
||||
|
||||
def print_drc_stats():
|
||||
debug.info(1,"DRC runs: {0}".format(num_drc_runs))
|
||||
def print_lvs_stats():
|
||||
|
|
|
|||
Loading…
Reference in New Issue