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Added change to route wmask en between driver and AND gates. Need to apply it to all cases.
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@@ -124,9 +124,9 @@ class write_mask_and_array(design.design):
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if i < self.num_wmasks-1:
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self.add_layout_pin(text="en",
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layer="metal3",
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offset=en_pin.bc(),
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width = self.en_width(i),
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height = drc('minwidth_metal3'))
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offset=en_pin.bc(),
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width = self.en_width(i),
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height = drc('minwidth_metal3'))
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wmask_out_pin = self.and2_insts[i].get_pin("Z")
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self.add_layout_pin(text="wmask_out_{0}".format(i),
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