mirror of https://github.com/VLSIDA/OpenRAM.git
Remove debug trace
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@ -61,7 +61,7 @@ class openram_test(unittest.TestCase):
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self.fail("LVS mismatch: {}".format(a.name))
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# For debug...
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import pdb; pdb.set_trace()
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#import pdb; pdb.set_trace()
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if OPTS.purge_temp:
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self.cleanup()
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