Refactor drc/lvs error output

compiler/base/hierarchy_design.py

@@ -7,15 +7,11 @@
 #
 import hierarchy_layout
 import hierarchy_spice
-import globals
 import verify
 import debug
 import os
 from globals import OPTS
-import graph_util
 
-total_drc_errors = 0 
-total_lvs_errors = 0
 
 class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
     """
@@ -51,14 +47,12 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
         # Final verification option does not allow nets to be connected by label.
         # Unit tests will check themselves.
         if OPTS.is_unit_test:
-            return
+            return ("skipped", "skipped")
         if not OPTS.check_lvsdrc:
-            return
+            return ("skipped", "skipped")
         # Do not run if disabled in options.
         if (OPTS.inline_lvsdrc or top_level):
 
-            global total_drc_errors
-            global total_lvs_errors
             tempspice = "{0}/{1}.sp".format(OPTS.openram_temp,self.name)
             tempgds = "{0}/{1}.gds".format(OPTS.openram_temp,self.name)
             self.sp_write(tempspice)
@@ -68,11 +62,11 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
             num_lvs_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification=final_verification) 
             debug.check(num_drc_errors == 0,"DRC failed for {0} with {1} error(s)".format(self.name,num_drc_errors))
             debug.check(num_lvs_errors == 0,"LVS failed for {0} with {1} errors(s)".format(self.name,num_lvs_errors))
-            total_drc_errors += num_drc_errors
-            total_lvs_errors += num_lvs_errors
 
             os.remove(tempspice)
             os.remove(tempgds)
+            
+            return (num_drc_errors, num_lvs_errors)
 
     def DRC(self, final_verification=False):
         """Checks DRC for a module"""
@@ -80,31 +74,35 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
         # Do not run if disabled in options.
 
         if (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)):
-            global total_drc_errors
             tempgds = "{0}/{1}.gds".format(OPTS.openram_temp,self.name)
             self.gds_write(tempgds)
             num_errors = verify.run_drc(self.name, tempgds, final_verification=final_verification)  
-            total_drc_errors += num_errors
             debug.check(num_errors == 0,"DRC failed for {0} with {1} error(s)".format(self.name,num_error))
 
             os.remove(tempgds)
 
+            return num_errors
+        else:
+            return "skipped"
+
     def LVS(self, final_verification=False):
         """Checks LVS for a module"""
         # Unit tests will check themselves.
         # Do not run if disabled in options.
 
         if (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)):
-            global total_lvs_errors
             tempspice = "{0}/{1}.sp".format(OPTS.openram_temp,self.name)
             tempgds = "{0}/{1}.gds".format(OPTS.openram_temp,self.name)
             self.sp_write(tempspice)
             self.gds_write(tempgds)
             num_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification=final_verification)
-            total_lvs_errors += num_errors
             debug.check(num_errors == 0,"LVS failed for {0} with {1} error(s)".format(self.name,num_errors))
             os.remove(tempspice)
-            os.remove(tempgds) 
+            os.remove(tempgds)
+
+            return num_errors
+        else:
+            return "skipped"
             
     def init_graph_params(self):
         """Initializes parameters relevant to the graph creation"""

compiler/characterizer/lib.py

@@ -621,17 +621,12 @@ class lib:
                         ))
 
         # information of checks
-        from hierarchy_design import total_drc_errors
+        (drc_errors, lvs_errors) = self.sram.DRC_LVS(final_verification=True, top_level=True)
-        from hierarchy_design import total_lvs_errors
+        datasheet.write("{0},{1},".format(drc_errors, lvs_errors))
-        DRC = 'skipped'
+        
-        LVS = 'skipped'
-        if OPTS.check_lvsdrc:
-            DRC = str(total_drc_errors)
-            LVS = str(total_lvs_errors)
-
-        datasheet.write("{0},{1},".format(DRC, LVS))
         # write area
-        datasheet.write(str(self.sram.width * self.sram.height)+',')
+        datasheet.write(str(self.sram.width * self.sram.height) + ',')
+        
         # write timing information for all ports
         for port in self.all_ports:
             #din timings

compiler/modules/hierarchical_decoder.py

@@ -25,8 +25,7 @@ class hierarchical_decoder(design.design):
         self.pre2x4_inst = []
         self.pre3x8_inst = []
 
-        b = factory.create(module_type="bitcell")
+        (self.cell_height, self.cell_multiple) = self.find_decoder_height()
-        self.cell_height = b.height
         self.rows = rows
         self.num_inputs = math.ceil(math.log(self.rows, 2))
         (self.no_of_pre2x4, self.no_of_pre3x8)=self.determine_predecodes(self.num_inputs)
@@ -35,6 +34,17 @@ class hierarchical_decoder(design.design):
         if not OPTS.netlist_only:
             self.create_layout()
 
+    def find_decoder_height(self):
+        b = factory.create(module_type="bitcell")
+
+        cell_height = b.height
+        and3 = factory.create(module_type="pand3",
+                              height=cell_height)
+        
+        # Try to make a nand with a given height
+        # Default
+        return (b.height, 1)
+        
     def create_netlist(self):
         self.add_modules()
         self.setup_netlist_constants()