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Fixed test issues, removed all bitcells not relevant for timing graph.

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Hunter Nichols
2019-05-15 17:17:26 -07:00
parent 178d3df5f5
commit a80698918b
3 changed files with 17 additions and 28 deletions
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compiler/tests/testutils.py
+1 -4
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@@ -62,11 +62,8 @@ class openram_test(unittest.TestCase):
"""
debug.info(1, "Finding feasible period for current test.")
delay_obj.set_load_slew(load, slew)
delay_obj.set_probe(probe_address="1"*sram.addr_size, probe_data=(sram.word_size-1))
test_port = delay_obj.read_ports[0] #Only test one port, assumes other ports have similar period.
delay_obj.create_signal_names()
delay_obj.create_measurement_names()
delay_obj.create_measurement_objects()
delay_obj.analysis_init(probe_address="1"*sram.addr_size, probe_data=(sram.word_size-1))
delay_obj.find_feasible_period_one_port(test_port)
return delay_obj.period