Fixed test issues, removed all bitcells not relevant for timing graph.

2026-08-29 17:39:02 +02:00 · 2019-05-15 17:17:26 -07:00
parent 178d3df5f5
commit a80698918b
3 changed files with 17 additions and 28 deletions
@@ -198,8 +198,9 @@ class bitcell_array(design.design):
        """Excludes bits in column from being added to graph except target"""
        #Function is not robust with column mux configurations
        for row in range(self.row_size):
-            if row == targ_row:
-                continue
-            self.graph_inst_exclude.add(self.cell_inst[row,targ_col])
+            for col in range(self.column_size):
+                if row == targ_row and col == targ_col:
+                    continue
+                self.graph_inst_exclude.add(self.cell_inst[row,col])