luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

falling_edge not negative_edge

This commit is contained in:
Matt Guthaus 2019-01-11 15:17:27 -08:00
parent 20b869f8e1
commit a7dd62b0e5
7 changed files with 7 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
compiler/characterizer/lib.py
View File

@ -329,7 +329,7 @@ class lib:
self.lib.write(" timing(){ \n") self.lib.write(" timing(){ \n")
self.lib.write(" timing_sense : non_unate; \n") self.lib.write(" timing_sense : non_unate; \n")
self.lib.write(" related_pin : \"clk{0}\"; \n".format(read_port)) self.lib.write(" related_pin : \"clk{0}\"; \n".format(read_port))
self.lib.write(" timing_type : negative_edge; \n") self.lib.write(" timing_type : falling_edge; \n")
self.lib.write(" cell_rise(CELL_TABLE) {\n") self.lib.write(" cell_rise(CELL_TABLE) {\n")
self.write_values(self.char_port_results[read_port]["delay_lh"],len(self.loads)," ") self.write_values(self.char_port_results[read_port]["delay_lh"],len(self.loads)," ")
self.lib.write(" }\n") # rise delay self.lib.write(" }\n") # rise delay

2
compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib
View File

@ -136,7 +136,7 @@ cell (sram_2_16_1_freepdk45){
timing(){ timing(){
timing_sense : non_unate; timing_sense : non_unate;
related_pin : "clk0"; related_pin : "clk0";
timing_type : rising_edge; timing_type : falling_edge;
cell_rise(CELL_TABLE) { cell_rise(CELL_TABLE) {
values("0.235, 0.235, 0.239",\ values("0.235, 0.235, 0.239",\
"0.235, 0.236, 0.24",\ "0.235, 0.236, 0.24",\

2
compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib
View File

@ -136,7 +136,7 @@ cell (sram_2_16_1_freepdk45){
timing(){ timing(){
timing_sense : non_unate; timing_sense : non_unate;
related_pin : "clk0"; related_pin : "clk0";
timing_type : rising_edge; timing_type : falling_edge;
cell_rise(CELL_TABLE) { cell_rise(CELL_TABLE) {
values("0.098, 0.098, 0.098",\ values("0.098, 0.098, 0.098",\
"0.098, 0.098, 0.098",\ "0.098, 0.098, 0.098",\

2
compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib
View File

@ -136,7 +136,7 @@ cell (sram_2_16_1_freepdk45){
timing(){ timing(){
timing_sense : non_unate; timing_sense : non_unate;
related_pin : "clk0"; related_pin : "clk0";
timing_type : rising_edge; timing_type : falling_edge;
cell_rise(CELL_TABLE) { cell_rise(CELL_TABLE) {
values("0.233, 0.233, 0.237",\ values("0.233, 0.233, 0.237",\
"0.233, 0.234, 0.237",\ "0.233, 0.234, 0.237",\

2
compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib
View File

@ -136,7 +136,7 @@ cell (sram_2_16_1_scn4m_subm){
timing(){ timing(){
timing_sense : non_unate; timing_sense : non_unate;
related_pin : "clk0"; related_pin : "clk0";
timing_type : rising_edge; timing_type : falling_edge;
cell_rise(CELL_TABLE) { cell_rise(CELL_TABLE) {
values("1.556, 1.576, 1.751",\ values("1.556, 1.576, 1.751",\
"1.559, 1.579, 1.754",\ "1.559, 1.579, 1.754",\

2
compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib
View File

@ -136,7 +136,7 @@ cell (sram_2_16_1_scn4m_subm){
timing(){ timing(){
timing_sense : non_unate; timing_sense : non_unate;
related_pin : "clk0"; related_pin : "clk0";
timing_type : rising_edge; timing_type : falling_edge;
cell_rise(CELL_TABLE) { cell_rise(CELL_TABLE) {
values("0.268, 0.268, 0.268",\ values("0.268, 0.268, 0.268",\
"0.268, 0.268, 0.268",\ "0.268, 0.268, 0.268",\

2
compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib
View File

@ -136,7 +136,7 @@ cell (sram_2_16_1_scn4m_subm){
timing(){ timing(){
timing_sense : non_unate; timing_sense : non_unate;
related_pin : "clk0"; related_pin : "clk0";
timing_type : rising_edge; timing_type : falling_edge;
cell_rise(CELL_TABLE) { cell_rise(CELL_TABLE) {
values("1.542, 1.562, 1.738",\ values("1.542, 1.562, 1.738",\
"1.545, 1.565, 1.741",\ "1.545, 1.565, 1.741",\