mirror of https://github.com/VLSIDA/OpenRAM.git
Rename omits 0 size ports
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24ee594e74
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a7246f5e7f
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@ -225,12 +225,17 @@ def read_config(config_file, is_unit_test=True):
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# If config didn't set output name, make a reasonable default.
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# If config didn't set output name, make a reasonable default.
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if (OPTS.output_name == ""):
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if (OPTS.output_name == ""):
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OPTS.output_name = "sram_{0}b_{1}w_{2}rw_{3}w_{4}r_{5}".format(OPTS.word_size,
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ports = ""
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OPTS.num_words,
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if OPTS.num_rw_ports>0:
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OPTS.num_rw_ports,
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ports += "{}rw_".format(OPTS.num_rw_ports)
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OPTS.num_w_ports,
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if OPTS.num_w_ports>0:
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OPTS.num_r_ports,
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ports += "{}w_".format(OPTS.num_w_ports)
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OPTS.tech_name)
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if OPTS.num_r_ports>0:
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ports += "{}r_".format(OPTS.num_r_ports)
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OPTS.output_name = "sram_{0}b_{1}_{2}{3}".format(OPTS.word_size,
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OPTS.num_words,
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ports,
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OPTS.tech_name)
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