mirror of https://github.com/VLSIDA/OpenRAM.git
Merged dev and fix conflicts in geometry.py
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commit
a711a5823d
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@ -143,7 +143,10 @@ class instance(geometry):
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self.rotate = rotate
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self.rotate = rotate
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self.offset = vector(offset).snap_to_grid()
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self.offset = vector(offset).snap_to_grid()
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self.mirror = mirror
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self.mirror = mirror
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if not OPTS.netlist_only:
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if OPTS.netlist_only:
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self.width = 0
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self.height = 0
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else:
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self.width = round_to_grid(mod.width)
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self.width = round_to_grid(mod.width)
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self.height = round_to_grid(mod.height)
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self.height = round_to_grid(mod.height)
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self.compute_boundary(offset,mirror,rotate)
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self.compute_boundary(offset,mirror,rotate)
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@ -267,7 +267,7 @@ class functional(simulation):
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t_intital=t_intital,
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t_intital=t_intital,
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t_final=t_final)
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t_final=t_final)
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self.stim.write_control(self.cycle_times[-1] + self.period)
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self.stim.write_control(self.cycle_times[-1] + self.period, runlvl=1)
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self.sf.close()
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self.sf.close()
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@ -232,8 +232,19 @@ class stimuli():
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measure_string=".meas tran {0} AVG v({1}) FROM={2}n TO={3}n\n\n".format(meas_name, dout, t_intital, t_final)
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measure_string=".meas tran {0} AVG v({1}) FROM={2}n TO={3}n\n\n".format(meas_name, dout, t_intital, t_final)
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self.sf.write(measure_string)
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self.sf.write(measure_string)
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def write_control(self, end_time):
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def write_control(self, end_time, runlvl=4):
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""" Write the control cards to run and end the simulation """
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""" Write the control cards to run and end the simulation """
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# These are guesses...
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if runlvl==1:
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reltol = 0.02 # 2%
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elif runlvl==2:
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reltol = 0.01 # 1%
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elif runlvl==3:
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reltol = 0.005 # 0.5%
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else:
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reltol = 0.001 # 0.1%
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# UIC is needed for ngspice to converge
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# UIC is needed for ngspice to converge
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self.sf.write(".TRAN 5p {0}n UIC\n".format(end_time))
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self.sf.write(".TRAN 5p {0}n UIC\n".format(end_time))
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if OPTS.spice_name == "ngspice":
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if OPTS.spice_name == "ngspice":
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@ -241,9 +252,9 @@ class stimuli():
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# which is more accurate, but slower than the default trapezoid method
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# which is more accurate, but slower than the default trapezoid method
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# Do not remove this or it may not converge due to some "pa_00" nodes
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# Do not remove this or it may not converge due to some "pa_00" nodes
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# unless you figure out what these are.
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# unless you figure out what these are.
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self.sf.write(".OPTIONS POST=1 RUNLVL=4 PROBE method=gear TEMP={}\n".format(self.temperature))
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self.sf.write(".OPTIONS POST=1 RELTOL={0} PROBE method=gear TEMP={1}\n".format(reltol,self.temperature))
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else:
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else:
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self.sf.write(".OPTIONS POST=1 RUNLVL=4 PROBE TEMP={}\n".format(self.temperature))
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self.sf.write(".OPTIONS POST=1 RUNLVL={0} PROBE TEMP={1}\n".format(runlvl,self.temperature))
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# create plots for all signals
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# create plots for all signals
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self.sf.write("* probe is used for hspice/xa, while plot is used in ngspice\n")
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self.sf.write("* probe is used for hspice/xa, while plot is used in ngspice\n")
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@ -11,12 +11,11 @@ import globals
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from globals import OPTS
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from globals import OPTS
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import debug
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import debug
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@unittest.skip("SKIPPING 22_psram_func_test")
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#@unittest.skip("SKIPPING 22_psram_func_test")
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class psram_func_test(openram_test):
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class psram_func_test(openram_test):
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def runTest(self):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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#OPTS.spice_name="hspice"
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OPTS.analytical_delay = False
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OPTS.analytical_delay = False
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OPTS.netlist_only = True
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OPTS.netlist_only = True
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OPTS.bitcell = "pbitcell"
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OPTS.bitcell = "pbitcell"
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@ -49,7 +48,7 @@ class psram_func_test(openram_test):
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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f = functional(s.s, tempspice, corner)
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f = functional(s.s, tempspice, corner)
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f.num_cycles = 5
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f.num_cycles = 10
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(fail,error) = f.run()
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(fail,error) = f.run()
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self.assertTrue(fail,error)
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self.assertTrue(fail,error)
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@ -11,13 +11,13 @@ import globals
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from globals import OPTS
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from globals import OPTS
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import debug
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import debug
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@unittest.skip("SKIPPING 22_sram_func_test")
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#@unittest.skip("SKIPPING 22_sram_func_test")
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class sram_func_test(openram_test):
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class sram_func_test(openram_test):
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def runTest(self):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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#OPTS.spice_name="hspice"
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OPTS.analytical_delay = False
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OPTS.analytical_delay = False
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OPTS.netlist_only = True
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# This is a hack to reload the characterizer __init__ with the spice version
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# This is a hack to reload the characterizer __init__ with the spice version
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from importlib import reload
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from importlib import reload
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