mirror of https://github.com/VLSIDA/OpenRAM.git
Passed freepdk45 tests with pdriver.py
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@ -12,9 +12,6 @@ class pdriver(pgate.pgate):
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This instantiates an even or odd number of inverters sized for driving a load.
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"""
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unique_id = 1
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inv_list = []
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inv_inst_list = []
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calc_size_list = []
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def __init__(self, height=None, name="", neg_polarity=False, c_load=8, size_list = []):
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@ -65,6 +62,7 @@ class pdriver(pgate.pgate):
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def same_polarity(self, num_stages):
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self.calc_size_list = []
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self.num_inv = num_stages
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# compute sizes
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c_prev = self.c_load
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@ -74,6 +72,7 @@ class pdriver(pgate.pgate):
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def diff_polarity(self, num_stages):
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self.calc_size_list = []
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# find which delay is smaller
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delay_below = ((num_stages-1)*(self.c_load**(1/num_stages-1))) + num_stages-1
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delay_above = ((num_stages+1)*(self.c_load**(1/num_stages+1))) + num_stages+1
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@ -93,6 +92,8 @@ class pdriver(pgate.pgate):
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def create_netlist(self):
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inv_list = []
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self.add_pins()
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self.add_modules()
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self.create_insts()
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@ -114,6 +115,7 @@ class pdriver(pgate.pgate):
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self.add_pin("gnd")
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def add_modules(self):
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self.inv_list = []
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if len(self.size_list) > 0: # size list specified
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for x in range(len(self.size_list)):
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self.inv_list.append(pinv(size=self.size_list[x], height=self.row_height))
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@ -125,6 +127,7 @@ class pdriver(pgate.pgate):
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def create_insts(self):
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self.inv_inst_list = []
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for x in range(1,self.num_inv+1):
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# Create first inverter
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if x == 1:
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