luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Passed freepdk45 tests with pdriver.py

This commit is contained in:
Jennifer Eve Sowash 2018-12-07 12:58:05 -08:00
parent a24e5229cb
commit a6eec10f41
1 changed files with 9 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
compiler/pgates/pdriver.py
View File

@ -12,9 +12,6 @@ class pdriver(pgate.pgate):
This instantiates an even or odd number of inverters sized for driving a load. This instantiates an even or odd number of inverters sized for driving a load.
""" """
unique_id = 1 unique_id = 1
inv_list = []
inv_inst_list = []
calc_size_list = []
def __init__(self, height=None, name="", neg_polarity=False, c_load=8, size_list = []): def __init__(self, height=None, name="", neg_polarity=False, c_load=8, size_list = []):
@ -65,6 +62,7 @@ class pdriver(pgate.pgate):
def same_polarity(self, num_stages): def same_polarity(self, num_stages):
self.calc_size_list = []
self.num_inv = num_stages self.num_inv = num_stages
# compute sizes # compute sizes
c_prev = self.c_load c_prev = self.c_load
@ -74,6 +72,7 @@ class pdriver(pgate.pgate):
def diff_polarity(self, num_stages): def diff_polarity(self, num_stages):
self.calc_size_list = []
# find which delay is smaller # find which delay is smaller
delay_below = ((num_stages-1)*(self.c_load**(1/num_stages-1))) + num_stages-1 delay_below = ((num_stages-1)*(self.c_load**(1/num_stages-1))) + num_stages-1
delay_above = ((num_stages+1)*(self.c_load**(1/num_stages+1))) + num_stages+1 delay_above = ((num_stages+1)*(self.c_load**(1/num_stages+1))) + num_stages+1
@ -93,6 +92,8 @@ class pdriver(pgate.pgate):
def create_netlist(self): def create_netlist(self):
inv_list = []
self.add_pins() self.add_pins()
self.add_modules() self.add_modules()
self.create_insts() self.create_insts()
@ -114,6 +115,7 @@ class pdriver(pgate.pgate):
self.add_pin("gnd") self.add_pin("gnd")
def add_modules(self): def add_modules(self):
self.inv_list = []
if len(self.size_list) > 0: # size list specified if len(self.size_list) > 0: # size list specified
for x in range(len(self.size_list)): for x in range(len(self.size_list)):
self.inv_list.append(pinv(size=self.size_list[x], height=self.row_height)) self.inv_list.append(pinv(size=self.size_list[x], height=self.row_height))
@ -125,6 +127,7 @@ class pdriver(pgate.pgate):
def create_insts(self): def create_insts(self):
self.inv_inst_list = []
for x in range(1,self.num_inv+1): for x in range(1,self.num_inv+1):
# Create first inverter # Create first inverter
if x == 1: if x == 1: