mirror of https://github.com/VLSIDA/OpenRAM.git
Skip riscv func test because too slow
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parent
1e24b780bb
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a62b82128c
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@ -15,7 +15,8 @@ from globals import OPTS
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from sram_factory import factory
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import debug
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#@unittest.skip("SKIPPING 50_riscv_func_test")
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@unittest.skip("SKIPPING 50_riscv_func_test")
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class riscv_func_test(openram_test):
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def runTest(self):
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@ -34,7 +35,7 @@ class riscv_func_test(openram_test):
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from importlib import reload
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import characterizer
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reload(characterizer)
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from characterizer import functional, delay
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from characterizer import functional
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from sram_config import sram_config
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c = sram_config(word_size=32,
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write_size=8,
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@ -15,6 +15,7 @@ from globals import OPTS
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from sram_factory import factory
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import debug
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#@unittest.skip("SKIPPING 50_riscv_phys_test")
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class riscv_phys_test(openram_test):
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