mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-29 01:24:39 +02:00
Merge remote-tracking branch 'openram_local/array_gen' into merge/full-array-gen-into-dev
# Conflicts: # technology/sky130/custom/sky130_col_cap_array.py
This commit is contained in:
Jesse Cirimelli-Low
@@ -1,731 +0,0 @@
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2023 Regents of the University of California, Santa Cruz
|
||||
# All rights reserved.
|
||||
#
|
||||
from openram import debug
|
||||
from openram.base import vector
|
||||
from openram.base import contact
|
||||
from openram.sram_factory import factory
|
||||
from openram.tech import drc, spice
|
||||
from openram.tech import cell_properties as props
|
||||
from openram import OPTS
|
||||
from openram.modules import bitcell_base_array
|
||||
|
||||
|
||||
class replica_bitcell_array(bitcell_base_array):
|
||||
"""
|
||||
Creates a bitcell array of cols x rows and then adds the replica
|
||||
and dummy columns and rows. Replica columns are on the left and
|
||||
right, respectively and connected to the given bitcell ports.
|
||||
Dummy are the outside columns/rows with WL and BL tied to gnd.
|
||||
Requires a regular bitcell array, replica bitcell, and dummy
|
||||
bitcell (BL/BR disconnected).
|
||||
"""
|
||||
def __init__(self, rows, cols, rbl=None, left_rbl=None, right_rbl=None, name=""):
|
||||
super().__init__(name=name, rows=rows, cols=cols, column_offset=0)
|
||||
debug.info(1, "Creating {0} {1} x {2} rbls: {3} left_rbl: {4} right_rbl: {5}".format(self.name,
|
||||
rows,
|
||||
cols,
|
||||
rbl,
|
||||
left_rbl,
|
||||
right_rbl))
|
||||
self.add_comment("rows: {0} cols: {1}".format(rows, cols))
|
||||
self.add_comment("rbl: {0} left_rbl: {1} right_rbl: {2}".format(rbl, left_rbl, right_rbl))
|
||||
|
||||
self.column_size = cols
|
||||
self.row_size = rows
|
||||
# This is how many RBLs are in all the arrays
|
||||
if rbl:
|
||||
self.rbl = rbl
|
||||
else:
|
||||
self.rbl=[1, 1 if len(self.all_ports)>1 else 0]
|
||||
# This specifies which RBL to put on the left or right
|
||||
# by port number
|
||||
# This could be an empty list
|
||||
if left_rbl != None:
|
||||
self.left_rbl = left_rbl
|
||||
else:
|
||||
self.left_rbl = [0]
|
||||
# This could be an empty list
|
||||
if right_rbl != None:
|
||||
self.right_rbl = right_rbl
|
||||
else:
|
||||
self.right_rbl=[1] if len(self.all_ports) > 1 else []
|
||||
self.rbls = self.left_rbl + self.right_rbl
|
||||
|
||||
debug.check(sum(self.rbl) == len(self.all_ports),
|
||||
"Invalid number of RBLs for port configuration.")
|
||||
debug.check(sum(self.rbl) >= len(self.left_rbl) + len(self.right_rbl),
|
||||
"Invalid number of RBLs for port configuration.")
|
||||
|
||||
# Two dummy rows plus replica even if we don't add the column
|
||||
self.extra_rows = sum(self.rbl)
|
||||
# Two dummy cols plus replica if we add the column
|
||||
self.extra_cols = len(self.left_rbl) + len(self.right_rbl)
|
||||
|
||||
# If we aren't using row/col caps, then we need to use the bitcell
|
||||
if not self.cell.end_caps:
|
||||
self.extra_rows += 2
|
||||
self.extra_cols += 2
|
||||
|
||||
self.create_netlist()
|
||||
if not OPTS.netlist_only:
|
||||
self.create_layout()
|
||||
|
||||
# We don't offset this because we need to align
|
||||
# the replica bitcell in the control logic
|
||||
# self.offset_all_coordinates()
|
||||
|
||||
def create_netlist(self):
|
||||
""" Create and connect the netlist """
|
||||
self.add_modules()
|
||||
self.add_pins()
|
||||
self.create_instances()
|
||||
|
||||
def add_modules(self):
|
||||
""" Array and dummy/replica columns
|
||||
|
||||
d or D = dummy cell (caps to distinguish grouping)
|
||||
r or R = replica cell (caps to distinguish grouping)
|
||||
b or B = bitcell
|
||||
replica columns 1
|
||||
v v
|
||||
bdDDDDDDDDDDDDDDdb <- Dummy row
|
||||
bdDDDDDDDDDDDDDDrb <- Dummy row
|
||||
br--------------rb
|
||||
br| Array |rb
|
||||
br| row x col |rb
|
||||
br--------------rb
|
||||
brDDDDDDDDDDDDDDdb <- Dummy row
|
||||
bdDDDDDDDDDDDDDDdb <- Dummy row
|
||||
|
||||
^^^^^^^^^^^^^^^
|
||||
dummy rows cols x 1
|
||||
|
||||
^ dummy columns ^
|
||||
1 x (rows + 4)
|
||||
"""
|
||||
# Bitcell array
|
||||
self.bitcell_array = factory.create(module_type="bitcell_array",
|
||||
column_offset=1 + len(self.left_rbl),
|
||||
cols=self.column_size,
|
||||
rows=self.row_size)
|
||||
|
||||
# Replica bitlines
|
||||
self.replica_columns = {}
|
||||
|
||||
for port in self.all_ports:
|
||||
if port in self.left_rbl:
|
||||
# We will always have self.rbl[0] rows of replica wordlines below
|
||||
# the array.
|
||||
# These go from the top (where the bitcell array starts ) down
|
||||
replica_bit = self.rbl[0] - port
|
||||
column_offset = self.rbl[0]
|
||||
|
||||
elif port in self.right_rbl:
|
||||
|
||||
# We will always have self.rbl[0] rows of replica wordlines below
|
||||
# the array.
|
||||
# These go from the bottom up
|
||||
replica_bit = self.rbl[0] + self.row_size + port
|
||||
column_offset = self.rbl[0] + self.column_size + 1
|
||||
else:
|
||||
continue
|
||||
|
||||
self.replica_columns[port] = factory.create(module_type="replica_column",
|
||||
rows=self.row_size,
|
||||
rbl=self.rbl,
|
||||
column_offset=column_offset,
|
||||
replica_bit=replica_bit)
|
||||
|
||||
# Dummy row
|
||||
self.dummy_row = factory.create(module_type="dummy_array",
|
||||
cols=self.column_size,
|
||||
rows=1,
|
||||
# dummy column + left replica column
|
||||
column_offset=1 + len(self.left_rbl),
|
||||
mirror=0)
|
||||
|
||||
# Dummy Row or Col Cap, depending on bitcell array properties
|
||||
col_cap_module_type = ("col_cap_array" if self.cell.end_caps else "dummy_array")
|
||||
self.col_cap_top = factory.create(module_type=col_cap_module_type,
|
||||
cols=self.column_size,
|
||||
rows=1,
|
||||
# dummy column + left replica column(s)
|
||||
column_offset=1 + len(self.left_rbl),
|
||||
mirror=0,
|
||||
location="top")
|
||||
|
||||
self.col_cap_bottom = factory.create(module_type=col_cap_module_type,
|
||||
cols=self.column_size,
|
||||
rows=1,
|
||||
# dummy column + left replica column(s)
|
||||
column_offset=1 + len(self.left_rbl),
|
||||
mirror=0,
|
||||
location="bottom")
|
||||
|
||||
# Dummy Col or Row Cap, depending on bitcell array properties
|
||||
row_cap_module_type = ("row_cap_array" if self.cell.end_caps else "dummy_array")
|
||||
|
||||
self.row_cap_left = factory.create(module_type=row_cap_module_type,
|
||||
cols=1,
|
||||
column_offset=0,
|
||||
rows=self.row_size + self.extra_rows,
|
||||
mirror=(self.rbl[0] + 1) % 2)
|
||||
|
||||
self.row_cap_right = factory.create(module_type=row_cap_module_type,
|
||||
cols=1,
|
||||
# dummy column
|
||||
# + left replica column(s)
|
||||
# + bitcell columns
|
||||
# + right replica column(s)
|
||||
column_offset=1 + len(self.left_rbl) + self.column_size + self.rbl[0],
|
||||
rows=self.row_size + self.extra_rows,
|
||||
mirror=(self.rbl[0] + 1) %2)
|
||||
|
||||
def add_pins(self):
|
||||
|
||||
# Arrays are always:
|
||||
# bitlines (column first then port order)
|
||||
# word lines (row first then port order)
|
||||
# dummy wordlines
|
||||
# replica wordlines
|
||||
# regular wordlines (bottom to top)
|
||||
# # dummy bitlines
|
||||
# replica bitlines (port order)
|
||||
# regular bitlines (left to right port order)
|
||||
#
|
||||
# vdd
|
||||
# gnd
|
||||
|
||||
self.add_bitline_pins()
|
||||
self.add_wordline_pins()
|
||||
self.add_pin("vdd", "POWER")
|
||||
self.add_pin("gnd", "GROUND")
|
||||
|
||||
def add_bitline_pins(self):
|
||||
# The bit is which port the RBL is for
|
||||
for bit in self.rbls:
|
||||
for port in self.all_ports:
|
||||
self.rbl_bitline_names[bit].append("rbl_bl_{0}_{1}".format(port, bit))
|
||||
for port in self.all_ports:
|
||||
self.rbl_bitline_names[bit].append("rbl_br_{0}_{1}".format(port, bit))
|
||||
# Make a flat list too
|
||||
self.all_rbl_bitline_names = [x for sl in self.rbl_bitline_names for x in sl]
|
||||
|
||||
self.bitline_names = self.bitcell_array.bitline_names
|
||||
# Make a flat list too
|
||||
self.all_bitline_names = [x for sl in zip(*self.bitline_names) for x in sl]
|
||||
|
||||
for port in self.left_rbl:
|
||||
self.add_pin_list(self.rbl_bitline_names[port], "INOUT")
|
||||
self.add_pin_list(self.all_bitline_names, "INOUT")
|
||||
for port in self.right_rbl:
|
||||
self.add_pin_list(self.rbl_bitline_names[port], "INOUT")
|
||||
|
||||
def add_wordline_pins(self):
|
||||
|
||||
# Wordlines to ground
|
||||
self.gnd_wordline_names = []
|
||||
|
||||
for port in self.all_ports:
|
||||
for bit in self.all_ports:
|
||||
self.rbl_wordline_names[port].append("rbl_wl_{0}_{1}".format(port, bit))
|
||||
if bit != port:
|
||||
self.gnd_wordline_names.append("rbl_wl_{0}_{1}".format(port, bit))
|
||||
|
||||
self.all_rbl_wordline_names = [x for sl in self.rbl_wordline_names for x in sl]
|
||||
|
||||
self.wordline_names = self.bitcell_array.wordline_names
|
||||
self.all_wordline_names = self.bitcell_array.all_wordline_names
|
||||
|
||||
# All wordlines including dummy and RBL
|
||||
self.replica_array_wordline_names = []
|
||||
self.replica_array_wordline_names.extend(["gnd"] * len(self.col_cap_top.get_wordline_names()))
|
||||
for bit in range(self.rbl[0]):
|
||||
self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[bit]])
|
||||
self.replica_array_wordline_names.extend(self.all_wordline_names)
|
||||
for bit in range(self.rbl[1]):
|
||||
self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[self.rbl[0] + bit]])
|
||||
self.replica_array_wordline_names.extend(["gnd"] * len(self.col_cap_top.get_wordline_names()))
|
||||
|
||||
for port in range(self.rbl[0]):
|
||||
self.add_pin(self.rbl_wordline_names[port][port], "INPUT")
|
||||
self.add_pin_list(self.all_wordline_names, "INPUT")
|
||||
for port in range(self.rbl[0], self.rbl[0] + self.rbl[1]):
|
||||
self.add_pin(self.rbl_wordline_names[port][port], "INPUT")
|
||||
|
||||
def create_instances(self):
|
||||
""" Create the module instances used in this design """
|
||||
self.supplies = ["vdd", "gnd"]
|
||||
|
||||
# Used for names/dimensions only
|
||||
self.cell = factory.create(module_type=OPTS.bitcell)
|
||||
|
||||
# Main array
|
||||
self.bitcell_array_inst=self.add_inst(name="bitcell_array",
|
||||
mod=self.bitcell_array)
|
||||
self.connect_inst(self.all_bitline_names + self.all_wordline_names + self.supplies)
|
||||
|
||||
# Replica columns
|
||||
self.replica_col_insts = []
|
||||
for port in self.all_ports:
|
||||
if port in self.rbls:
|
||||
self.replica_col_insts.append(self.add_inst(name="replica_col_{}".format(port),
|
||||
mod=self.replica_columns[port]))
|
||||
self.connect_inst(self.rbl_bitline_names[port] + self.replica_array_wordline_names + self.supplies)
|
||||
else:
|
||||
self.replica_col_insts.append(None)
|
||||
|
||||
# Dummy rows under the bitcell array (connected with with the replica cell wl)
|
||||
self.dummy_row_replica_insts = []
|
||||
# Note, this is the number of left and right even if we aren't adding the columns to this bitcell array!
|
||||
for port in self.all_ports:
|
||||
self.dummy_row_replica_insts.append(self.add_inst(name="dummy_row_{}".format(port),
|
||||
mod=self.dummy_row))
|
||||
self.connect_inst(self.all_bitline_names + [x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[port]] + self.supplies)
|
||||
|
||||
# Top/bottom dummy rows or col caps
|
||||
self.dummy_row_insts = []
|
||||
self.dummy_row_insts.append(self.add_inst(name="dummy_row_bot",
|
||||
mod=self.col_cap_bottom))
|
||||
self.connect_inst(self.all_bitline_names + ["gnd"] * len(self.col_cap_bottom.get_wordline_names()) + self.supplies)
|
||||
self.dummy_row_insts.append(self.add_inst(name="dummy_row_top",
|
||||
mod=self.col_cap_top))
|
||||
self.connect_inst(self.all_bitline_names + ["gnd"] * len(self.col_cap_top.get_wordline_names()) + self.supplies)
|
||||
|
||||
# Left/right Dummy columns
|
||||
self.dummy_col_insts = []
|
||||
self.dummy_col_insts.append(self.add_inst(name="dummy_col_left",
|
||||
mod=self.row_cap_left))
|
||||
self.connect_inst(["dummy_left_" + bl for bl in self.row_cap_left.all_bitline_names] + self.replica_array_wordline_names + self.supplies)
|
||||
self.dummy_col_insts.append(self.add_inst(name="dummy_col_right",
|
||||
mod=self.row_cap_right))
|
||||
self.connect_inst(["dummy_right_" + bl for bl in self.row_cap_right.all_bitline_names] + self.replica_array_wordline_names + self.supplies)
|
||||
|
||||
def create_layout(self):
|
||||
|
||||
# This creates space for the unused wordline connections as well as the
|
||||
# row-based or column based power and ground lines.
|
||||
self.vertical_pitch = 1.1 * getattr(self, "{}_pitch".format(self.supply_stack[0]))
|
||||
self.horizontal_pitch = 1.1 * getattr(self, "{}_pitch".format(self.supply_stack[2]))
|
||||
self.unused_offset = vector(0.25, 0.25)
|
||||
|
||||
# This is a bitcell x bitcell offset to scale
|
||||
self.bitcell_offset = vector(self.cell.width, self.cell.height)
|
||||
self.col_end_offset = vector(self.cell.width, self.cell.height)
|
||||
self.row_end_offset = vector(self.cell.width, self.cell.height)
|
||||
|
||||
# Everything is computed with the main array
|
||||
self.bitcell_array_inst.place(offset=self.unused_offset)
|
||||
|
||||
self.add_replica_columns()
|
||||
|
||||
self.add_end_caps()
|
||||
|
||||
# Array was at (0, 0) but move everything so it is at the lower left
|
||||
# We move DOWN the number of left RBL even if we didn't add the column to this bitcell array
|
||||
# Note that this doesn't include the row/col cap
|
||||
array_offset = self.bitcell_offset.scale(1 + len(self.left_rbl), 1 + self.rbl[0])
|
||||
self.translate_all(array_offset.scale(-1, -1))
|
||||
|
||||
# Add extra width on the left and right for the unused WLs
|
||||
|
||||
self.width = self.dummy_col_insts[1].rx() + self.unused_offset.x
|
||||
self.height = self.dummy_row_insts[1].uy()
|
||||
|
||||
self.add_layout_pins()
|
||||
|
||||
self.route_supplies()
|
||||
|
||||
self.route_unused_wordlines()
|
||||
|
||||
lower_left = self.find_lowest_coords()
|
||||
upper_right = self.find_highest_coords()
|
||||
self.width = upper_right.x - lower_left.x
|
||||
self.height = upper_right.y - lower_left.y
|
||||
self.translate_all(lower_left)
|
||||
|
||||
self.add_boundary()
|
||||
|
||||
self.DRC_LVS()
|
||||
|
||||
def get_main_array_top(self):
|
||||
""" Return the top of the main bitcell array. """
|
||||
return self.bitcell_array_inst.uy()
|
||||
|
||||
def get_main_array_bottom(self):
|
||||
""" Return the bottom of the main bitcell array. """
|
||||
return self.bitcell_array_inst.by()
|
||||
|
||||
def get_main_array_left(self):
|
||||
""" Return the left of the main bitcell array. """
|
||||
return self.bitcell_array_inst.lx()
|
||||
|
||||
def get_main_array_right(self):
|
||||
""" Return the right of the main bitcell array. """
|
||||
return self.bitcell_array_inst.rx()
|
||||
|
||||
def get_replica_top(self):
|
||||
""" Return the top of all replica columns. """
|
||||
return self.dummy_row_insts[0].by()
|
||||
|
||||
def get_replica_bottom(self):
|
||||
""" Return the bottom of all replica columns. """
|
||||
return self.dummy_row_insts[0].uy()
|
||||
|
||||
def get_replica_left(self):
|
||||
""" Return the left of all replica columns. """
|
||||
return self.dummy_col_insts[0].rx()
|
||||
|
||||
def get_replica_right(self):
|
||||
""" Return the right of all replica columns. """
|
||||
return self.dummy_col_insts[1].rx()
|
||||
|
||||
def get_column_offsets(self):
|
||||
"""
|
||||
Return an array of the x offsets of all the regular bits
|
||||
"""
|
||||
offsets = [x + self.bitcell_array_inst.lx() for x in self.bitcell_array.get_column_offsets()]
|
||||
return offsets
|
||||
|
||||
def add_replica_columns(self):
|
||||
""" Add replica columns on left and right of array """
|
||||
|
||||
# Grow from left to right, toward the array
|
||||
for bit, port in enumerate(self.left_rbl):
|
||||
offset = self.bitcell_offset.scale(-len(self.left_rbl) + bit, -self.rbl[0] - 1) + self.unused_offset
|
||||
self.replica_col_insts[bit].place(offset)
|
||||
# Grow to the right of the bitcell array, array outward
|
||||
for bit, port in enumerate(self.right_rbl):
|
||||
offset = self.bitcell_array_inst.lr() + self.bitcell_offset.scale(bit, -self.rbl[0] - 1)
|
||||
self.replica_col_insts[self.rbl[0] + bit].place(offset)
|
||||
|
||||
# Replica dummy rows
|
||||
# Add the dummy rows even if we aren't adding the replica column to this bitcell array
|
||||
# These grow up, toward the array
|
||||
for bit in range(self.rbl[0]):
|
||||
dummy_offset = self.bitcell_offset.scale(0, -self.rbl[0] + bit + (-self.rbl[0] + bit) % 2) + self.unused_offset
|
||||
self.dummy_row_replica_insts[bit].place(offset=dummy_offset,
|
||||
mirror="MX" if (-self.rbl[0] + bit) % 2 else "R0")
|
||||
# These grow up, away from the array
|
||||
for bit in range(self.rbl[1]):
|
||||
dummy_offset = self.bitcell_offset.scale(0, bit + bit % 2) + self.bitcell_array_inst.ul()
|
||||
self.dummy_row_replica_insts[self.rbl[0] + bit].place(offset=dummy_offset,
|
||||
mirror="MX" if (self.row_size + bit) % 2 else "R0")
|
||||
|
||||
def add_end_caps(self):
|
||||
""" Add dummy cells or end caps around the array """
|
||||
|
||||
# Far top dummy row (first row above array is NOT flipped if even number of rows)
|
||||
flip_dummy = (self.row_size + self.rbl[1]) % 2
|
||||
dummy_row_offset = self.bitcell_offset.scale(0, self.rbl[1] + flip_dummy) + self.bitcell_array_inst.ul()
|
||||
self.dummy_row_insts[1].place(offset=dummy_row_offset,
|
||||
mirror="MX" if flip_dummy else "R0")
|
||||
|
||||
# Far bottom dummy row (first row below array IS flipped)
|
||||
flip_dummy = (self.rbl[0] + 1) % 2
|
||||
dummy_row_offset = self.bitcell_offset.scale(0, -self.rbl[0] - 1 + flip_dummy) + self.unused_offset
|
||||
self.dummy_row_insts[0].place(offset=dummy_row_offset,
|
||||
mirror="MX" if flip_dummy else "R0")
|
||||
# Far left dummy col
|
||||
# Shifted down by the number of left RBLs even if we aren't adding replica column to this bitcell array
|
||||
dummy_col_offset = self.bitcell_offset.scale(-len(self.left_rbl) - 1, -self.rbl[0] - 1) + self.unused_offset
|
||||
self.dummy_col_insts[0].place(offset=dummy_col_offset)
|
||||
|
||||
# Far right dummy col
|
||||
# Shifted down by the number of left RBLs even if we aren't adding replica column to this bitcell array
|
||||
dummy_col_offset = self.bitcell_offset.scale(len(self.right_rbl), -self.rbl[0] - 1) + self.bitcell_array_inst.lr()
|
||||
self.dummy_col_insts[1].place(offset=dummy_col_offset)
|
||||
|
||||
def add_layout_pins(self):
|
||||
""" Add the layout pins """
|
||||
|
||||
# All wordlines
|
||||
# Main array wl and bl/br
|
||||
for pin_name in self.all_wordline_names:
|
||||
pin_list = self.bitcell_array_inst.get_pins(pin_name)
|
||||
for pin in pin_list:
|
||||
self.add_layout_pin(text=pin_name,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(0, 1),
|
||||
width=self.width,
|
||||
height=pin.height())
|
||||
|
||||
# Replica wordlines (go by the row instead of replica column because we may have to add a pin
|
||||
# even though the column is in another local bitcell array)
|
||||
for (names, inst) in zip(self.rbl_wordline_names, self.dummy_row_replica_insts):
|
||||
for (wl_name, pin_name) in zip(names, self.dummy_row.get_wordline_names()):
|
||||
if wl_name in self.gnd_wordline_names:
|
||||
continue
|
||||
pin = inst.get_pin(pin_name)
|
||||
self.add_layout_pin(text=wl_name,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(0, 1),
|
||||
width=self.width,
|
||||
height=pin.height())
|
||||
|
||||
for pin_name in self.all_bitline_names:
|
||||
pin_list = self.bitcell_array_inst.get_pins(pin_name)
|
||||
for pin in pin_list:
|
||||
self.add_layout_pin(text=pin_name,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(1, 0),
|
||||
width=pin.width(),
|
||||
height=self.height)
|
||||
|
||||
# Replica bitlines
|
||||
if len(self.rbls) > 0:
|
||||
for (names, inst) in zip(self.rbl_bitline_names, self.replica_col_insts):
|
||||
pin_names = self.replica_columns[self.rbls[0]].all_bitline_names
|
||||
for (bl_name, pin_name) in zip(names, pin_names):
|
||||
pin = inst.get_pin(pin_name)
|
||||
self.add_layout_pin(text=bl_name,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(1, 0),
|
||||
width=pin.width(),
|
||||
height=self.height)
|
||||
|
||||
def route_supplies(self):
|
||||
|
||||
if OPTS.bitcell == "pbitcell":
|
||||
bitcell = factory.create(module_type="pbitcell")
|
||||
else:
|
||||
bitcell = getattr(props, "bitcell_{}port".format(OPTS.num_ports))
|
||||
|
||||
vdd_dir = bitcell.vdd_dir
|
||||
gnd_dir = bitcell.gnd_dir
|
||||
|
||||
# vdd/gnd are only connected in the perimeter cells
|
||||
supply_insts = self.dummy_col_insts + self.dummy_row_insts
|
||||
|
||||
# For the wordlines
|
||||
top_bot_mult = 1
|
||||
left_right_mult = 1
|
||||
|
||||
# There are always vertical pins for the WLs on the left/right if we have unused wordlines
|
||||
self.left_gnd_locs = self.route_side_pin("gnd", "left", left_right_mult)
|
||||
self.right_gnd_locs = self.route_side_pin("gnd","right", left_right_mult)
|
||||
# This needs to be big enough so that they aren't in the same supply routing grid
|
||||
left_right_mult = 4
|
||||
|
||||
if gnd_dir == "V":
|
||||
self.top_gnd_locs = self.route_side_pin("gnd", "top", top_bot_mult)
|
||||
self.bot_gnd_locs = self.route_side_pin("gnd", "bot", top_bot_mult)
|
||||
# This needs to be big enough so that they aren't in the same supply routing grid
|
||||
top_bot_mult = 4
|
||||
|
||||
if vdd_dir == "V":
|
||||
self.top_vdd_locs = self.route_side_pin("vdd", "top", top_bot_mult)
|
||||
self.bot_vdd_locs = self.route_side_pin("vdd", "bot", top_bot_mult)
|
||||
elif vdd_dir == "H":
|
||||
self.left_vdd_locs = self.route_side_pin("vdd", "left", left_right_mult)
|
||||
self.right_vdd_locs = self.route_side_pin("vdd", "right", left_right_mult)
|
||||
else:
|
||||
debug.error("Invalid vdd direction {}".format(vdd_dir), -1)
|
||||
|
||||
|
||||
for inst in supply_insts:
|
||||
for pin in inst.get_pins("vdd"):
|
||||
if vdd_dir == "V":
|
||||
self.connect_side_pin(pin, "top", self.top_vdd_locs[0].y)
|
||||
self.connect_side_pin(pin, "bot", self.bot_vdd_locs[0].y)
|
||||
elif vdd_dir == "H":
|
||||
self.connect_side_pin(pin, "left", self.left_vdd_locs[0].x)
|
||||
self.connect_side_pin(pin, "right", self.right_vdd_locs[0].x)
|
||||
|
||||
|
||||
for inst in supply_insts:
|
||||
for pin in inst.get_pins("gnd"):
|
||||
if gnd_dir == "V":
|
||||
self.connect_side_pin(pin, "top", self.top_gnd_locs[0].y)
|
||||
self.connect_side_pin(pin, "bot", self.bot_gnd_locs[0].y)
|
||||
elif gnd_dir == "H":
|
||||
self.connect_side_pin(pin, "left", self.left_gnd_locs[0].x)
|
||||
self.connect_side_pin(pin, "right", self.right_gnd_locs[0].x)
|
||||
|
||||
|
||||
def route_unused_wordlines(self):
|
||||
""" Connect the unused RBL and dummy wordlines to gnd """
|
||||
# This grounds all the dummy row word lines
|
||||
for inst in self.dummy_row_insts:
|
||||
for wl_name in self.col_cap_top.get_wordline_names():
|
||||
pin = inst.get_pin(wl_name)
|
||||
self.connect_side_pin(pin, "left", self.left_gnd_locs[0].x)
|
||||
self.connect_side_pin(pin, "right", self.right_gnd_locs[0].x)
|
||||
|
||||
# Ground the unused replica wordlines
|
||||
for (names, inst) in zip(self.rbl_wordline_names, self.dummy_row_replica_insts):
|
||||
for (wl_name, pin_name) in zip(names, self.dummy_row.get_wordline_names()):
|
||||
if wl_name in self.gnd_wordline_names:
|
||||
pin = inst.get_pin(pin_name)
|
||||
self.connect_side_pin(pin, "left", self.left_gnd_locs[0].x)
|
||||
self.connect_side_pin(pin, "right", self.right_gnd_locs[0].x)
|
||||
|
||||
def route_side_pin(self, name, side, offset_multiple=1):
|
||||
"""
|
||||
Routes a vertical or horizontal pin on the side of the bbox.
|
||||
The multiple specifies how many track offsets to be away from the side assuming
|
||||
(0,0) (self.width, self.height)
|
||||
"""
|
||||
if side in ["left", "right"]:
|
||||
return self.route_vertical_side_pin(name, side, offset_multiple)
|
||||
elif side in ["top", "bottom", "bot"]:
|
||||
return self.route_horizontal_side_pin(name, side, offset_multiple)
|
||||
else:
|
||||
debug.error("Invalid side {}".format(side), -1)
|
||||
|
||||
def route_vertical_side_pin(self, name, side, offset_multiple=1):
|
||||
"""
|
||||
Routes a vertical pin on the side of the bbox.
|
||||
"""
|
||||
if side == "left":
|
||||
bot_loc = vector(-offset_multiple * self.vertical_pitch, 0)
|
||||
top_loc = vector(-offset_multiple * self.vertical_pitch, self.height)
|
||||
elif side == "right":
|
||||
bot_loc = vector(self.width + offset_multiple * self.vertical_pitch, 0)
|
||||
top_loc = vector(self.width + offset_multiple * self.vertical_pitch, self.height)
|
||||
|
||||
layer = self.supply_stack[2]
|
||||
top_via = contact(layer_stack=self.supply_stack,
|
||||
directions=("H", "H"))
|
||||
|
||||
|
||||
# self.add_layout_pin_rect_ends(text=name,
|
||||
# layer=layer,
|
||||
# start=bot_loc,
|
||||
# end=top_loc)
|
||||
self.add_layout_pin_segment_center(text=name,
|
||||
layer=layer,
|
||||
start=bot_loc,
|
||||
end=top_loc,
|
||||
width=top_via.second_layer_width)
|
||||
|
||||
return (bot_loc, top_loc)
|
||||
|
||||
def route_horizontal_side_pin(self, name, side, offset_multiple=1):
|
||||
"""
|
||||
Routes a horizontal pin on the side of the bbox.
|
||||
"""
|
||||
if side in ["bottom", "bot"]:
|
||||
left_loc = vector(0, -offset_multiple * self.horizontal_pitch)
|
||||
right_loc = vector(self.width, -offset_multiple * self.horizontal_pitch)
|
||||
elif side == "top":
|
||||
left_loc = vector(0, self.height + offset_multiple * self.horizontal_pitch)
|
||||
right_loc = vector(self.width, self.height + offset_multiple * self.horizontal_pitch)
|
||||
|
||||
layer = self.supply_stack[0]
|
||||
side_via = contact(layer_stack=self.supply_stack,
|
||||
directions=("V", "V"))
|
||||
|
||||
# self.add_layout_pin_rect_ends(text=name,
|
||||
# layer=layer,
|
||||
# start=left_loc,
|
||||
# end=right_loc)
|
||||
self.add_layout_pin_segment_center(text=name,
|
||||
layer=layer,
|
||||
start=left_loc,
|
||||
end=right_loc,
|
||||
width=side_via.first_layer_height)
|
||||
|
||||
return (left_loc, right_loc)
|
||||
|
||||
def connect_side_pin(self, pin, side, offset):
|
||||
"""
|
||||
Used to connect horizontal layers of pins to the left/right straps
|
||||
locs provides the offsets of the pin strip end points.
|
||||
"""
|
||||
if side in ["left", "right"]:
|
||||
self.connect_vertical_side_pin(pin, side, offset)
|
||||
elif side in ["top", "bottom", "bot"]:
|
||||
self.connect_horizontal_side_pin(pin, side, offset)
|
||||
else:
|
||||
debug.error("Invalid side {}".format(side), -1)
|
||||
|
||||
def connect_horizontal_side_pin(self, pin, side, yoffset):
|
||||
"""
|
||||
Used to connect vertical layers of pins to the top/bottom horizontal straps
|
||||
"""
|
||||
cell_loc = pin.center()
|
||||
pin_loc = vector(cell_loc.x, yoffset)
|
||||
|
||||
# Place the pins a track outside of the array
|
||||
self.add_via_stack_center(offset=pin_loc,
|
||||
from_layer=pin.layer,
|
||||
to_layer=self.supply_stack[0],
|
||||
directions=("V", "V"))
|
||||
|
||||
# Add a path to connect to the array
|
||||
self.add_path(pin.layer, [cell_loc, pin_loc])
|
||||
|
||||
|
||||
def connect_vertical_side_pin(self, pin, side, xoffset):
|
||||
"""
|
||||
Used to connect vertical layers of pins to the top/bottom vertical straps
|
||||
"""
|
||||
cell_loc = pin.center()
|
||||
pin_loc = vector(xoffset, cell_loc.y)
|
||||
|
||||
# Place the pins a track outside of the array
|
||||
self.add_via_stack_center(offset=pin_loc,
|
||||
from_layer=pin.layer,
|
||||
to_layer=self.supply_stack[2],
|
||||
directions=("H", "H"))
|
||||
|
||||
# Add a path to connect to the array
|
||||
self.add_path(pin.layer, [cell_loc, pin_loc])
|
||||
|
||||
def analytical_power(self, corner, load):
|
||||
"""Power of Bitcell array and bitline in nW."""
|
||||
# Dynamic Power from Bitline
|
||||
bl_wire = self.gen_bl_wire()
|
||||
cell_load = 2 * bl_wire.return_input_cap()
|
||||
bl_swing = OPTS.rbl_delay_percentage
|
||||
freq = spice["default_event_frequency"]
|
||||
bitline_dynamic = self.calc_dynamic_power(corner, cell_load, freq, swing=bl_swing)
|
||||
|
||||
# Calculate the bitcell power which currently only includes leakage
|
||||
cell_power = self.cell.analytical_power(corner, load)
|
||||
|
||||
# Leakage power grows with entire array and bitlines.
|
||||
total_power = self.return_power(cell_power.dynamic + bitline_dynamic * self.column_size,
|
||||
cell_power.leakage * self.column_size * self.row_size)
|
||||
return total_power
|
||||
|
||||
|
||||
def gen_bl_wire(self):
|
||||
if OPTS.netlist_only:
|
||||
height = 0
|
||||
else:
|
||||
height = self.height
|
||||
bl_pos = 0
|
||||
bl_wire = self.generate_rc_net(int(self.row_size - bl_pos), height, drc("minwidth_m1"))
|
||||
bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c # 1 access tx d/s per cell
|
||||
return bl_wire
|
||||
|
||||
def graph_exclude_bits(self, targ_row=None, targ_col=None):
|
||||
"""
|
||||
Excludes bits in column from being added to graph except target
|
||||
"""
|
||||
self.bitcell_array.graph_exclude_bits(targ_row, targ_col)
|
||||
|
||||
def graph_exclude_replica_col_bits(self):
|
||||
"""
|
||||
Exclude all replica/dummy cells in the replica columns except the replica bit.
|
||||
"""
|
||||
|
||||
for port in self.left_rbl + self.right_rbl:
|
||||
self.replica_columns[port].exclude_all_but_replica()
|
||||
|
||||
def get_cell_name(self, inst_name, row, col):
|
||||
"""
|
||||
Gets the spice name of the target bitcell.
|
||||
"""
|
||||
return self.bitcell_array.get_cell_name(inst_name + "{}x".format(OPTS.hier_seperator) + self.bitcell_array_inst.name, row, col)
|
||||
|
||||
def clear_exclude_bits(self):
|
||||
"""
|
||||
Clears the bit exclusions
|
||||
"""
|
||||
self.bitcell_array.init_graph_params()
|
||||
@@ -6,7 +6,7 @@
|
||||
#
|
||||
|
||||
from openram import debug
|
||||
from openram.modules import bitcell_base
|
||||
from openram.modules.bitcell_base import bitcell_base
|
||||
from openram.tech import cell_properties as props
|
||||
|
||||
|
||||
@@ -23,6 +23,10 @@ class sky130_bitcell(bitcell_base):
|
||||
cell_name = "sky130_fd_bd_sram__sram_sp_cell_opt1"
|
||||
elif version == "opt1a":
|
||||
cell_name = "sky130_fd_bd_sram__sram_sp_cell_opt1a"
|
||||
elif version == "opt1_noblcon":
|
||||
cell_name = "sky130_fd_bd_sram__openram_sp_cell_opt1_noblcon"
|
||||
elif version == "opt1a_noblcon":
|
||||
cell_name = "sky130_fd_bd_sram__openram_sp_cell_opt1a_noblcon"
|
||||
else:
|
||||
debug.error("Invalid sky130 cell name", -1)
|
||||
|
||||
|
||||
@@ -6,88 +6,84 @@
|
||||
#
|
||||
|
||||
from openram import debug
|
||||
from openram.modules import bitcell_array
|
||||
from openram.modules.bitcell_array import bitcell_array
|
||||
from openram.modules import pattern
|
||||
from openram.sram_factory import factory
|
||||
from openram.base import geometry
|
||||
from openram import OPTS
|
||||
from .sky130_bitcell_base_array import sky130_bitcell_base_array
|
||||
|
||||
from math import ceil
|
||||
|
||||
class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array):
|
||||
"""
|
||||
Creates a rows x cols array of memory cells.
|
||||
Assumes bit-lines and word lines are connected by abutment.
|
||||
"""
|
||||
def __init__(self, rows, cols, column_offset=0, name=""):
|
||||
# Don't call the regular bitcell_array constructor since we don't want its constructor, just
|
||||
# some of it's useful member functions
|
||||
sky130_bitcell_base_array.__init__(self, rows=rows, cols=cols, column_offset=column_offset, name=name)
|
||||
if self.row_size % 2 == 0:
|
||||
debug.error("Invalid number of rows {}. number of rows (excluding dummy rows) must be odd to connect to col ends".format(self.row_size), -1)
|
||||
debug.info(1, "Creating {0} {1} x {2}".format(self.name, self.row_size, self.column_size))
|
||||
self.add_comment("rows: {0} cols: {1}".format(self.row_size, self.column_size))
|
||||
|
||||
# This will create a default set of bitline/wordline names
|
||||
self.create_all_bitline_names()
|
||||
self.create_all_wordline_names()
|
||||
self.create_netlist()
|
||||
if not OPTS.netlist_only:
|
||||
self.create_layout()
|
||||
self.add_supply_pins()
|
||||
|
||||
def __init__(self, rows, cols, column_offset=0, row_offset=0, name="", left_rbl=None, right_rbl=None):
|
||||
super().__init__(rows=rows, cols=cols, column_offset=column_offset, row_offset=row_offset, name=name)
|
||||
self.left_rbl = left_rbl
|
||||
self.right_rbl = right_rbl
|
||||
self.column_offset = column_offset
|
||||
self.row_offset = row_offset
|
||||
def add_modules(self):
|
||||
""" Add the modules used in this design """
|
||||
# Bitcell for port names only
|
||||
self.cell = factory.create(module_type=OPTS.bitcell, version="opt1")
|
||||
self.cell2 = factory.create(module_type=OPTS.bitcell, version="opt1a")
|
||||
self.cella = factory.create(module_type=OPTS.bitcell, version="opt1a")
|
||||
#self.cell_noblcon = factory.create(module_type=OPTS.bitcell, version="opt1_noblcon")
|
||||
#self.cella_noblcon = factory.create(module_type=OPTS.bitcell, version="opt1a_noblcon")
|
||||
self.strap = factory.create(module_type="internal", version="wlstrap")
|
||||
self.strap2 = factory.create(module_type="internal", version="wlstrap_p")
|
||||
self.strap3 = factory.create(module_type="internal", version="wlstrapa")
|
||||
self.strap4 = factory.create(module_type="internal", version="wlstrapa_p")
|
||||
self.strap_p = factory.create(module_type="internal", version="wlstrap_p")
|
||||
self.strapa = factory.create(module_type="internal", version="wlstrapa")
|
||||
self.strapa_p = factory.create(module_type="internal", version="wlstrapa_p")
|
||||
|
||||
def create_instances(self):
|
||||
""" Create the module instances used in this design """
|
||||
self.cell_inst = {}
|
||||
self.array_layout = []
|
||||
alternate_bitcell = (self.row_size) % 2
|
||||
for row in range(0, self.row_size):
|
||||
self.all_inst={}
|
||||
self.cell_inst={}
|
||||
|
||||
#self.cell_noblcon_inst = geometry.instance("cell_noblcon_inst", mod=self.cell_noblcon, is_bitcell=True)
|
||||
#self.cella_noblcon_inst = geometry.instance("cella_noblcon_inst", mod=self.cella_noblcon, is_bitcell=True)
|
||||
|
||||
row_layout = []
|
||||
bit_row_opt1 = [geometry.instance("00_opt1", mod=self.cell, is_bitcell=True, mirror='MX')] \
|
||||
+ [geometry.instance("01_strap_p", mod=self.strap, is_bitcell=False, mirror='MX')]\
|
||||
+ [geometry.instance("02_opt1", mod=self.cell, is_bitcell=True, mirror='XY')] \
|
||||
+ [geometry.instance("03_strap", mod=self.strap_p, is_bitcell=False, mirror='MX')]
|
||||
|
||||
bit_row_opt1a = [geometry.instance("10_opt1a", mod=self.cella, is_bitcell=True)] \
|
||||
+ [geometry.instance("11_strapa", mod=self.strap, is_bitcell=False)] \
|
||||
+ [geometry.instance("12_opt1a", mod=self.cella, is_bitcell=True, mirror='MY')] \
|
||||
+ [geometry.instance("13_strapa_p", mod=self.strapa_p, is_bitcell=False)]
|
||||
|
||||
bit_block = []
|
||||
if self.row_offset % 2 == 0:
|
||||
pattern.append_row_to_block(bit_block, bit_row_opt1)
|
||||
pattern.append_row_to_block(bit_block, bit_row_opt1a)
|
||||
else:
|
||||
pattern.append_row_to_block(bit_block, bit_row_opt1a)
|
||||
pattern.append_row_to_block(bit_block, bit_row_opt1)
|
||||
|
||||
alternate_strap = (self.row_size+1) % 2
|
||||
for col in range(0, self.column_size):
|
||||
if alternate_bitcell == 1:
|
||||
row_layout.append(self.cell)
|
||||
self.cell_inst[row, col]=self.add_inst(name="row_{}_col_{}_bitcell".format(row, col),
|
||||
mod=self.cell)
|
||||
else:
|
||||
row_layout.append(self.cell2)
|
||||
self.cell_inst[row, col]=self.add_inst(name="row_{}_col_{}_bitcell".format(row, col),
|
||||
mod=self.cell2)
|
||||
self.connect_inst(self.get_bitcell_pins(row, col))
|
||||
if col != self.column_size - 1:
|
||||
if alternate_strap:
|
||||
if row % 2:
|
||||
name="row_{}_col_{}_wlstrapa_p".format(row, col)
|
||||
row_layout.append(self.strap4)
|
||||
self.add_inst(name=name, mod=self.strap4)
|
||||
else:
|
||||
name="row_{}_col_{}_wlstrap_p".format(row, col)
|
||||
row_layout.append(self.strap2)
|
||||
self.add_inst(name=name, mod=self.strap2)
|
||||
alternate_strap = 0
|
||||
else:
|
||||
if row % 2:
|
||||
name="row_{}_col_{}_wlstrapa".format(row, col)
|
||||
row_layout.append(self.strap3)
|
||||
self.add_inst(name=name.format(row, col), mod=self.strap3)
|
||||
else:
|
||||
name="row_{}_col_{}_wlstrap".format(row, col)
|
||||
row_layout.append(self.strap)
|
||||
self.add_inst(name=name.format(row, col), mod=self.strap)
|
||||
alternate_strap = 1
|
||||
self.connect_inst(self.get_strap_pins(row, col, name))
|
||||
if alternate_bitcell == 0:
|
||||
alternate_bitcell = 1
|
||||
else:
|
||||
alternate_bitcell = 0
|
||||
self.array_layout.append(row_layout)
|
||||
for row in bit_block:
|
||||
row = pattern.rotate_list(row, self.column_offset * 2)
|
||||
|
||||
self.pattern = pattern(self, "bitcell_array", bit_block, num_rows=self.row_size, num_cols=self.column_size, num_cores_x=ceil(self.column_size/2), num_cores_y=ceil(self.row_size/2), name_template="bit_r{0}_c{1}")
|
||||
|
||||
self.pattern.connect_array()
|
||||
|
||||
# for i in range(len(self.insts)):
|
||||
# if self.left_rbl:
|
||||
# if "r{}".format(self.row_size-1) in self.insts[i].name:
|
||||
# if self.insts[i].mod == self.cell:
|
||||
# self.insts[i].mod = self.cell_noblcon_inst.mod
|
||||
# self.insts[i].gds = self.cell_noblcon_inst.gds
|
||||
# elif self.insts[i].mod == self.cella:
|
||||
# self.insts[i].mod = self.cella_noblcon_inst.mod
|
||||
# self.insts[i].gds = self.cella_noblcon_inst.gds
|
||||
# if self.right_rbl:
|
||||
# if "r{}".format("0") in self.insts[i].name:
|
||||
# if self.insts[i].mod == self.cell:
|
||||
# self.insts[i].mod = self.cell_noblcon_inst.mod
|
||||
# self.insts[i].gds = self.cell_noblcon_inst.gds
|
||||
# elif self.insts[i].mod == self.cella:
|
||||
# self.insts[i].mod = self.cella_noblcon_inst.mod
|
||||
# self.insts[i].gds = self.cella_noblcon_inst.gds
|
||||
|
||||
@@ -11,56 +11,18 @@ from openram.modules import bitcell_base_array
|
||||
from openram.sram_factory import factory
|
||||
from openram.tech import layer
|
||||
from openram import OPTS
|
||||
|
||||
from openram.modules import pattern
|
||||
|
||||
class sky130_bitcell_base_array(bitcell_base_array):
|
||||
"""
|
||||
Abstract base class for bitcell-arrays -- bitcell, dummy, replica
|
||||
"""
|
||||
def __init__(self, name, rows, cols, column_offset):
|
||||
super().__init__(name, rows, cols, column_offset)
|
||||
def __init__(self, name, rows, cols, column_offset, row_offset):
|
||||
super().__init__(name, rows, cols, column_offset, row_offset)
|
||||
debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols))
|
||||
|
||||
self.cell = factory.create(module_type=OPTS.bitcell, version="opt1")
|
||||
|
||||
def place_array(self, name_template, row_offset=0, col_offset=0):
|
||||
yoffset = 0.0
|
||||
|
||||
for row in range(0, len(self.array_layout)):
|
||||
xoffset = 0.0
|
||||
for col in range(0, len(self.array_layout[row])):
|
||||
self.place_inst = self.insts[(col) + (row) * len(self.array_layout[row])]
|
||||
|
||||
if row % 2 == 0:
|
||||
if col == 0:
|
||||
self.place_inst.place(offset=[xoffset, yoffset + self.cell.height], mirror="MX")
|
||||
elif col % 4 == 0:
|
||||
self.place_inst.place(offset=[xoffset, yoffset + self.cell.height], mirror="MX")
|
||||
elif col % 4 == 3 :
|
||||
self.place_inst.place(offset=[xoffset, yoffset + self.cell.height], mirror="MX")
|
||||
elif col % 4 == 2:
|
||||
self.place_inst.place(offset=[xoffset + self.cell.width, yoffset + self.cell.height], mirror="XY")
|
||||
else:
|
||||
self.place_inst.place(offset=[xoffset, yoffset + self.cell.height], mirror="MX")
|
||||
else:
|
||||
if col == 0:
|
||||
self.place_inst.place(offset=[xoffset, yoffset])
|
||||
elif col % 4 == 0:
|
||||
self.place_inst.place(offset=[xoffset, yoffset])
|
||||
elif col % 4 == 3 :
|
||||
self.place_inst.place(offset=[xoffset, yoffset])
|
||||
elif col % 4 == 2:
|
||||
self.place_inst.place(offset=[xoffset + self.cell.width, yoffset], mirror="MY")
|
||||
# self.place_inst.place(offset=[xoffset, yoffset])
|
||||
else:
|
||||
self.place_inst.place(offset=[xoffset, yoffset])
|
||||
|
||||
xoffset += self.place_inst.width
|
||||
yoffset += self.place_inst.height
|
||||
|
||||
self.width = max([x.rx() for x in self.insts])
|
||||
self.height = max([x.uy() for x in self.insts])
|
||||
|
||||
def get_bitcell_pins(self, row, col, swap = False):
|
||||
"""
|
||||
Creates a list of connections in the bitcell,
|
||||
@@ -123,66 +85,36 @@ class sky130_bitcell_base_array(bitcell_base_array):
|
||||
strap_pins = ["vdd", "gnd", "vdd"]
|
||||
return strap_pins
|
||||
|
||||
def add_supply_pins(self):
|
||||
""" Add the layout pins """
|
||||
def route_supplies(self):
|
||||
# Copy a vdd/gnd layout pin from every cell
|
||||
|
||||
super().route_supplies()
|
||||
for inst in self.insts:
|
||||
if "wlstrap" in inst.name:
|
||||
if "VPWR" in inst.mod.pins:
|
||||
self.copy_layout_pin(inst, "VPWR", "vdd")
|
||||
if "VGND" in inst.mod.pins:
|
||||
self.copy_layout_pin(inst, "VGND", "gnd")
|
||||
if "VPWR" in inst.mod.pins:
|
||||
self.copy_layout_pin(inst, "VPWR", "vdd")
|
||||
if "VGND" in inst.mod.pins:
|
||||
self.copy_layout_pin(inst, "VGND", "gnd")
|
||||
|
||||
for row in range(self.row_size):
|
||||
for col in range(self.column_size):
|
||||
inst = self.cell_inst[row, col]
|
||||
for pin_name in ["vdd", "gnd"]:
|
||||
self.copy_layout_pin(inst, pin_name)
|
||||
if hasattr(self, 'cell_inst'):
|
||||
for col in range(self.column_size):
|
||||
inst = self.cell_inst[0,col]
|
||||
pin = inst.get_pin("vpb")
|
||||
self.objs.append(geometry.rectangle(layer["nwell"],
|
||||
pin.ll(),
|
||||
pin.width(),
|
||||
pin.height()))
|
||||
self.objs.append(geometry.label("vdd", layer["nwell"], pin.center()))
|
||||
|
||||
try:
|
||||
from openram.tech import layer_override
|
||||
if layer_override['VNB']:
|
||||
pin = inst.get_pin("vnb")
|
||||
self.objs.append(geometry.label("gnd", layer["pwellp"], pin.center()))
|
||||
self.objs.append(geometry.rectangle(layer["pwellp"],
|
||||
pin.ll(),
|
||||
pin.width(),
|
||||
pin.height()))
|
||||
except:
|
||||
pin = inst.get_pin("vnb")
|
||||
self.add_label("vdd", pin.layer, pin.center())
|
||||
|
||||
if row == 2: #add only 1 label per col
|
||||
|
||||
if 'VPB' or 'vpb' in self.cell_inst[row, col].mod.pins:
|
||||
pin = inst.get_pin("vpb")
|
||||
self.objs.append(geometry.rectangle(layer["nwell"],
|
||||
pin.ll(),
|
||||
pin.width(),
|
||||
pin.height()))
|
||||
self.objs.append(geometry.label("vdd", layer["nwell"], pin.center()))
|
||||
|
||||
if 'VNB' or 'vnb'in self.cell_inst[row, col].mod.pins:
|
||||
try:
|
||||
from openram.tech import layer_override
|
||||
if layer_override['VNB']:
|
||||
pin = inst.get_pin("vnb")
|
||||
self.objs.append(geometry.label("gnd", layer["pwellp"], pin.center()))
|
||||
self.objs.append(geometry.rectangle(layer["pwellp"],
|
||||
pin.ll(),
|
||||
pin.width(),
|
||||
pin.height()))
|
||||
except:
|
||||
pin = inst.get_pin("vnb")
|
||||
self.add_label("vdd", pin.layer, pin.center())
|
||||
|
||||
def add_bitline_pins(self):
|
||||
bitline_names = self.cell.get_all_bitline_names()
|
||||
for col in range(self.column_size):
|
||||
for port in self.all_ports:
|
||||
bl_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port])
|
||||
text = "bl_{0}_{1}".format(port, col)
|
||||
#if "Y" in self.cell_inst[0, col].mirror:
|
||||
# text = text.replace("bl", "br")
|
||||
self.add_layout_pin(text=text,
|
||||
layer=bl_pin.layer,
|
||||
offset=bl_pin.ll().scale(1, 0),
|
||||
width=bl_pin.width(),
|
||||
height=self.height)
|
||||
br_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port + 1])
|
||||
text = "br_{0}_{1}".format(port, col)
|
||||
#if "Y" in self.cell_inst[0, col].mirror:
|
||||
# text = text.replace("br", "bl")
|
||||
self.add_layout_pin(text=text,
|
||||
layer=br_pin.layer,
|
||||
offset=br_pin.ll().scale(1, 0),
|
||||
width=br_pin.width(),
|
||||
height=self.height)
|
||||
|
||||
@@ -7,213 +7,199 @@
|
||||
from openram import debug
|
||||
from openram.base import vector
|
||||
from openram.base import contact
|
||||
from openram import debug
|
||||
from openram.base import round_to_grid
|
||||
from openram.sram_factory import factory
|
||||
from openram.tech import drc, spice
|
||||
from openram.tech import cell_properties as props
|
||||
from openram import OPTS
|
||||
from openram.modules.capped_replica_bitcell_array import capped_replica_bitcell_array
|
||||
from .sky130_bitcell_base_array import sky130_bitcell_base_array
|
||||
from math import sqrt
|
||||
|
||||
|
||||
class sky130_capped_replica_bitcell_array(sky130_bitcell_base_array):
|
||||
class sky130_capped_replica_bitcell_array(capped_replica_bitcell_array, sky130_bitcell_base_array):
|
||||
"""
|
||||
Creates a replica bitcell array then adds the row and column caps to all
|
||||
sides of a bitcell array.
|
||||
"""
|
||||
def __init__(self, rows, cols, rbl=None, left_rbl=None, right_rbl=None, name=""):
|
||||
super().__init__(name, rows, cols, column_offset=0)
|
||||
debug.info(1, "Creating {0} {1} x {2} rbls: {3} left_rbl: {4} right_rbl: {5}".format(self.name,
|
||||
rows,
|
||||
cols,
|
||||
rbl,
|
||||
left_rbl,
|
||||
right_rbl))
|
||||
self.add_comment("rows: {0} cols: {1}".format(rows, cols))
|
||||
self.add_comment("rbl: {0} left_rbl: {1} right_rbl: {2}".format(rbl, left_rbl, right_rbl))
|
||||
super().__init__(rows, cols, rbl, left_rbl, right_rbl, name)
|
||||
|
||||
def route_power_ring(self, v_layer, h_layer):
|
||||
# ring is manually added and routed in add_layout_pins
|
||||
pass
|
||||
|
||||
# This is how many RBLs are in all the arrays
|
||||
self.rbl = rbl
|
||||
# This specifies which RBL to put on the left or right by port number
|
||||
# This could be an empty list
|
||||
if left_rbl is not None:
|
||||
self.left_rbl = left_rbl
|
||||
else:
|
||||
self.left_rbl = []
|
||||
# This could be an empty list
|
||||
if right_rbl is not None:
|
||||
self.right_rbl = right_rbl
|
||||
else:
|
||||
self.right_rbl = []
|
||||
def add_layout_pins(self):
|
||||
""" Add the layout pins """
|
||||
|
||||
self.create_netlist()
|
||||
if not OPTS.netlist_only:
|
||||
self.create_layout()
|
||||
for row_end in self.dummy_col_insts:
|
||||
row_end = row_end.mod
|
||||
print(self.get_all_wordline_names(), row_end.get_wordline_names())
|
||||
for (rba_wl_name, wl_name) in zip(self.get_all_wordline_names(), row_end.get_wordline_names()):
|
||||
pin = row_end.get_pin(wl_name)
|
||||
self.add_layout_pin(text=rba_wl_name,
|
||||
layer=pin.layer,
|
||||
offset=vector(0,pin.ll().scale(0, 1)[1]),
|
||||
#width=self.width,
|
||||
width=pin.width(),
|
||||
height=pin.height())
|
||||
|
||||
def create_netlist(self):
|
||||
""" Create and connect the netlist """
|
||||
self.add_modules()
|
||||
self.add_pins()
|
||||
self.create_instances()
|
||||
pin_height = (round_to_grid(drc["minarea_m3"] / round_to_grid(sqrt(drc["minarea_m3"]))) + drc["{0}_to_{0}".format('m3')])
|
||||
drc_width = drc["{0}_to_{0}".format('m3')]
|
||||
|
||||
def add_modules(self):
|
||||
self.replica_bitcell_array = factory.create(module_type="replica_bitcell_array",
|
||||
cols=self.column_size,
|
||||
rows=self.row_size,
|
||||
rbl=self.rbl,
|
||||
left_rbl=self.left_rbl,
|
||||
right_rbl=self.right_rbl)
|
||||
# vdd/gnd are only connected in the perimeter cells
|
||||
# replica column should only have a vdd/gnd in the dummy cell on top/bottom
|
||||
supply_insts = self.dummy_row_insts
|
||||
|
||||
def add_pins(self):
|
||||
|
||||
# Arrays are always:
|
||||
# bitlines (column first then port order)
|
||||
# word lines (row first then port order)
|
||||
# dummy wordlines
|
||||
# replica wordlines
|
||||
# regular wordlines (bottom to top)
|
||||
# # dummy bitlines
|
||||
# replica bitlines (port order)
|
||||
# regular bitlines (left to right port order)
|
||||
#
|
||||
# vdd
|
||||
# gnd
|
||||
|
||||
self.add_bitline_pins()
|
||||
self.add_wordline_pins()
|
||||
self.add_pin("vdd", "POWER")
|
||||
self.add_pin("gnd", "GROUND")
|
||||
|
||||
def add_bitline_pins(self):
|
||||
self.bitline_names = self.replica_bitcell_array.bitline_names
|
||||
self.all_bitline_names = self.replica_bitcell_array.all_bitline_names
|
||||
self.rbl_bitline_names = self.replica_bitcell_array.rbl_bitline_names
|
||||
self.all_rbl_bitline_names = self.replica_bitcell_array.all_rbl_bitline_names
|
||||
|
||||
self.bitline_pins = []
|
||||
|
||||
for port in self.left_rbl:
|
||||
self.bitline_pins.extend(self.rbl_bitline_names[port])
|
||||
self.bitline_pins.extend(self.all_bitline_names)
|
||||
for port in self.right_rbl:
|
||||
self.bitline_pins.extend(self.rbl_bitline_names[port])
|
||||
|
||||
self.add_pin_list(self.bitline_pins, "INOUT")
|
||||
|
||||
def add_wordline_pins(self):
|
||||
# some of these are just included for compatibility with modules instantiating this module
|
||||
self.rbl_wordline_names = self.replica_bitcell_array.rbl_wordline_names
|
||||
self.all_rbl_wordline_names = self.replica_bitcell_array.all_rbl_wordline_names
|
||||
self.wordline_names = self.replica_bitcell_array.wordline_names
|
||||
self.all_wordline_names = self.replica_bitcell_array.all_wordline_names
|
||||
|
||||
self.wordline_pins = []
|
||||
|
||||
for port in range(self.rbl[0]):
|
||||
self.wordline_pins.append(self.rbl_wordline_names[port][port])
|
||||
self.wordline_pins.extend(self.all_wordline_names)
|
||||
for port in range(self.rbl[0], self.rbl[0] + self.rbl[1]):
|
||||
self.wordline_pins.append(self.rbl_wordline_names[port][port])
|
||||
|
||||
self.add_pin_list(self.wordline_pins, "INPUT")
|
||||
|
||||
def create_instances(self):
|
||||
""" Create the module instances used in this design """
|
||||
self.supplies = ["vdd", "gnd"]
|
||||
|
||||
# Main array
|
||||
self.replica_bitcell_array_inst=self.add_inst(name="replica_bitcell_array",
|
||||
mod=self.replica_bitcell_array)
|
||||
self.connect_inst(self.bitline_pins + self.wordline_pins + self.supplies)
|
||||
|
||||
def create_layout(self):
|
||||
|
||||
self.replica_bitcell_array_inst.place(offset=0)
|
||||
|
||||
self.width = self.replica_bitcell_array.width
|
||||
self.height = self.replica_bitcell_array.height
|
||||
|
||||
for pin_name in self.bitline_pins + self.wordline_pins + self.supplies:
|
||||
self.copy_layout_pin(self.replica_bitcell_array_inst, pin_name)
|
||||
|
||||
self.add_boundary()
|
||||
|
||||
self.DRC_LVS()
|
||||
|
||||
def get_main_array_top(self):
|
||||
return self.replica_bitcell_array.get_main_array_top()
|
||||
|
||||
def get_main_array_bottom(self):
|
||||
return self.replica_bitcell_array.get_main_array_bottom()
|
||||
|
||||
def get_main_array_left(self):
|
||||
return self.replica_bitcell_array.get_main_array_left()
|
||||
|
||||
def get_main_array_right(self):
|
||||
return self.replica_bitcell_array.get_main_array_right()
|
||||
|
||||
def get_replica_top(self):
|
||||
return self.replica_bitcell_array.get_replica_top()
|
||||
|
||||
def get_replica_bottom(self):
|
||||
return self.replica_bitcell_array.get_replica_bottom()
|
||||
|
||||
def get_replica_left(self):
|
||||
return self.replica_bitcell_array.get_replica_left()
|
||||
|
||||
def get_replica_right(self):
|
||||
return self.replica_bitcell_array.get_replica_right()
|
||||
for pin_name in self.supplies:
|
||||
for supply_inst in supply_insts:
|
||||
vdd_alternate = 0
|
||||
gnd_alternate = 0
|
||||
for cell_inst in supply_inst.mod.insts:
|
||||
inst = cell_inst.mod
|
||||
for pin in inst.get_pins(pin_name):
|
||||
if pin.name == 'vdd':
|
||||
if vdd_alternate:
|
||||
connection_offset = -0.02
|
||||
vdd_alternate = 0
|
||||
else:
|
||||
connection_offset = 0.02
|
||||
vdd_alternate = 1
|
||||
connection_width = drc["minwidth_{}".format('m1')]
|
||||
track_offset = 1
|
||||
elif pin.name == 'gnd':
|
||||
if gnd_alternate:
|
||||
connection_offset = 0.00
|
||||
gnd_alternate = 0
|
||||
else:
|
||||
connection_offset = 0.00
|
||||
gnd_alternate = 1
|
||||
connection_width = drc["minwidth_{}".format('m1')]
|
||||
track_offset = 4
|
||||
pin_width = round_to_grid(sqrt(drc["minarea_m3"]))
|
||||
pin_height = round_to_grid(drc["minarea_m3"] / pin_width)
|
||||
if inst.cell_name == 'sky130_fd_bd_sram__sram_sp_colend_p_cent' or inst.cell_name == 'sky130_fd_bd_sram__sram_sp_colenda_p_cent' or inst.cell_name == 'sky130_fd_bd_sram__sram_sp_colend_cent' or inst.cell_name == 'sky130_fd_bd_sram__sram_sp_colenda_cent' or 'corner' in inst.cell_name:
|
||||
if 'dummy_row_bot' in supply_inst.name:
|
||||
pin_center = vector(pin.center()[0], -1 * track_offset * (pin_height + drc_width*2))
|
||||
self.add_segment_center(pin.layer, pin_center+supply_inst.ll()+cell_inst.ll()+vector(connection_offset,0), vector((pin_center+supply_inst.ll()+cell_inst.ll())[0] + connection_offset, 0), connection_width)
|
||||
elif 'dummy_row_top' in supply_inst.name:
|
||||
pin_center = vector(pin.center()[0],inst.height + 1 * track_offset* (pin_height + drc_width*2))
|
||||
self.add_segment_center(pin.layer, pin_center+supply_inst.ll()+cell_inst.ll()+vector(connection_offset,0), vector((pin_center+supply_inst.ll()+cell_inst.ll())[0] + connection_offset, self.height), connection_width)
|
||||
# elif 'replica_col' in supply_inst.name and cell_inst.mirror == 'MX':
|
||||
# pin_center = vector(pin.center()[0], -1 * track_offset* (pin_height + drc_width*2))
|
||||
# self.add_segment_center(pin.layer, pin_center+supply_inst.ll()+cell_inst.ll()+vector(connection_offset,0), vector((pin_center+supply_inst.ll()+cell_inst.ll())[0] + connection_offset, 0), connection_width)
|
||||
# elif 'replica_col' in supply_inst.name:
|
||||
# pin_center = vector(pin.center()[0],inst.height + 1 * track_offset * (pin_height + drc_width*2))
|
||||
# self.add_segment_center(pin.layer, pin_center+supply_inst.ll()+cell_inst.ll()+vector(connection_offset,0), vector((pin_center+supply_inst.ll()+cell_inst.ll())[0] + connection_offset,self.height), connection_width)
|
||||
self.add_via_stack_center(from_layer=pin.layer,
|
||||
to_layer='m2',
|
||||
offset=pin_center+supply_inst.ll()+cell_inst.ll() + vector(connection_offset,0))
|
||||
|
||||
|
||||
def get_column_offsets(self):
|
||||
return self.replica_bitcell_array.get_column_offsets()
|
||||
# add well contacts to perimeter cells
|
||||
for pin_name in ['vpb', 'vnb']:
|
||||
for supply_inst in supply_insts:
|
||||
vnb_alternate = 0
|
||||
vpb_alternate = 0
|
||||
for cell_inst in supply_inst.mod.insts:
|
||||
|
||||
def analytical_power(self, corner, load):
|
||||
"""Power of Bitcell array and bitline in nW."""
|
||||
# Dynamic Power from Bitline
|
||||
bl_wire = self.gen_bl_wire()
|
||||
cell_load = 2 * bl_wire.return_input_cap()
|
||||
bl_swing = OPTS.rbl_delay_percentage
|
||||
freq = spice["default_event_frequency"]
|
||||
bitline_dynamic = self.calc_dynamic_power(corner, cell_load, freq, swing=bl_swing)
|
||||
inst = cell_inst.mod
|
||||
for pin in inst.get_pins(pin_name):
|
||||
if pin.name == 'vpb':
|
||||
if vpb_alternate:
|
||||
connection_offset = 0.01
|
||||
vpb_alternate = 0
|
||||
else:
|
||||
connection_offset = 0.02
|
||||
vpb_alternate = 1
|
||||
connection_width = drc["minwidth_{}".format('m1')]
|
||||
track_offset = 2
|
||||
elif pin.name == 'vnb':
|
||||
if vnb_alternate:
|
||||
connection_offset = -0.01
|
||||
vnb_alternate = 0
|
||||
else:
|
||||
connection_offset = -0.02
|
||||
vnb_alternate = 1
|
||||
connection_width = drc["minwidth_{}".format('m1')]
|
||||
track_offset = 3
|
||||
if inst.cell_name == 'sky130_fd_bd_sram__sram_sp_colend_p_cent' or inst.cell_name == 'sky130_fd_bd_sram__sram_sp_colenda_p_cent' or inst.cell_name == 'sky130_fd_bd_sram__sram_sp_colend_cent' or inst.cell_name == 'sky130_fd_bd_sram__sram_sp_colenda_cent':
|
||||
if 'dummy_row_bot' in supply_inst.name:
|
||||
pin_center = vector(pin.center()[0], -1 * track_offset * (pin_height + drc_width*2))
|
||||
self.add_segment_center(pin.layer, pin_center+supply_inst.ll()+cell_inst.ll()+vector(connection_offset,0), vector((pin_center+supply_inst.ll()+cell_inst.ll())[0] + connection_offset, 0), connection_width)
|
||||
elif 'dummy_row_top' in supply_inst.name:
|
||||
pin_center = vector(pin.center()[0],inst.height + 1 * track_offset* (pin_height + drc_width*2))
|
||||
self.add_segment_center(pin.layer, pin_center+supply_inst.ll()+cell_inst.ll()+vector(connection_offset,0), vector((pin_center+supply_inst.ll()+cell_inst.ll())[0] + connection_offset, self.height), connection_width)
|
||||
# elif 'replica_col' in supply_inst.name:
|
||||
# pin_center = vector(pin.center()[0], -1 * track_offset* (pin_height + drc_width*2))
|
||||
# self.add_segment_center(pin.layer, pin_center+supply_inst.ll()+cell_inst.ll()+vector(connection_offset,0), vector((pin_center+supply_inst.ll()+cell_inst.ll())[0] + connection_offset, 0), connection_width)
|
||||
# elif 'replica_col' in supply_inst.name:
|
||||
# pin_center = vector(pin.center()[0],inst.height + 1 * track_offset * (pin_height + drc_width*2))
|
||||
# self.add_segment_center(pin.layer, pin_center+supply_inst.ll()+cell_inst.ll()+vector(connection_offset,0), vector((pin_center+supply_inst.ll()+cell_inst.ll())[0] + connection_offset,self.height), connection_width)
|
||||
self.add_via_stack_center(from_layer=pin.layer,
|
||||
to_layer='m2',
|
||||
offset=pin_center+supply_inst.ll()+cell_inst.ll() + vector(connection_offset,0))
|
||||
|
||||
# Calculate the bitcell power which currently only includes leakage
|
||||
cell_power = self.cell.analytical_power(corner, load)
|
||||
min_area = drc["minarea_{}".format('m3')]
|
||||
for track,supply, offset in zip(range(1,5),['vdd','vdd','gnd','gnd'],[min_area * 6,min_area * 6, 0, 0]):
|
||||
y_offset = track * (pin_height + drc_width*2)
|
||||
self.add_segment_center('m2', vector(-0.4,-y_offset), vector(self.width+0.4, -y_offset), drc["minwidth_{}".format('m2')])
|
||||
self.add_segment_center('m2', vector(-0.4,self.height + y_offset), vector(self.width+0.4, self.height + y_offset), drc["minwidth_{}".format('m2')])
|
||||
self.add_power_pin(name=supply,
|
||||
loc=vector(round_to_grid(sqrt(min_area))/2 + offset, -y_offset),
|
||||
start_layer='m2')
|
||||
self.add_power_pin(name=supply,
|
||||
loc=vector(round_to_grid(sqrt(min_area))/2 + offset, self.height + y_offset),
|
||||
start_layer='m2')
|
||||
self.add_power_pin(name=supply,
|
||||
loc=vector(self.width - round_to_grid(sqrt(min_area))/2 - offset, -y_offset),
|
||||
start_layer='m2')
|
||||
self.add_power_pin(name=supply,
|
||||
loc=vector(self.width - round_to_grid(sqrt(min_area))/2 - offset, self.height + y_offset),
|
||||
start_layer='m2')
|
||||
|
||||
# Leakage power grows with entire array and bitlines.
|
||||
total_power = self.return_power(cell_power.dynamic + bitline_dynamic * self.column_size,
|
||||
cell_power.leakage * self.column_size * self.row_size)
|
||||
return total_power
|
||||
self.offset_all_coordinates()
|
||||
self.height = self.height + self.dummy_col_insts[0].lr().y * 2
|
||||
|
||||
|
||||
|
||||
def gen_bl_wire(self):
|
||||
if OPTS.netlist_only:
|
||||
height = 0
|
||||
else:
|
||||
height = self.height
|
||||
bl_pos = 0
|
||||
bl_wire = self.generate_rc_net(int(self.row_size - bl_pos), height, drc("minwidth_m1"))
|
||||
bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c # 1 access tx d/s per cell
|
||||
return bl_wire
|
||||
|
||||
def graph_exclude_bits(self, targ_row=None, targ_col=None):
|
||||
"""
|
||||
Excludes bits in column from being added to graph except target
|
||||
"""
|
||||
self.replica_bitcell_array.graph_exclude_bits(targ_row, targ_col)
|
||||
|
||||
def graph_exclude_replica_col_bits(self):
|
||||
"""
|
||||
Exclude all replica/dummy cells in the replica columns except the replica bit.
|
||||
"""
|
||||
self.replica_bitcell_array.graph_exclude_replica_col_bits()
|
||||
|
||||
def get_cell_name(self, inst_name, row, col):
|
||||
"""
|
||||
Gets the spice name of the target bitcell.
|
||||
"""
|
||||
return self.replica_bitcell_array.get_cell_name(inst_name + "{}x".format(OPTS.hier_seperator) + self.replica_bitcell_array_inst.name, row, col)
|
||||
|
||||
def clear_exclude_bits(self):
|
||||
"""
|
||||
Clears the bit exclusions
|
||||
"""
|
||||
self.replica_bitcell_array.clear_exclude_bits()
|
||||
for pin_name in self.bitline_pin_list:
|
||||
pin_list = self.replica_bitcell_array_inst.get_pins(pin_name)
|
||||
for pin in pin_list:
|
||||
if 'bl' in pin.name:
|
||||
self.add_layout_pin(text=pin_name,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(1, 0),
|
||||
width=pin.width(),
|
||||
height=self.height)
|
||||
elif 'br' in pin_name:
|
||||
self.add_layout_pin(text=pin_name,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(1, 0) + vector(0,pin_height + drc_width*2),
|
||||
width=pin.width(),
|
||||
height=self.height - 2 *(pin_height + drc_width*2))
|
||||
|
||||
# # Replica bitlines
|
||||
# if len(self.rbls) > 0:
|
||||
# for (names, inst) in zip(self.rbl_bitline_names, self.replica_col_insts):
|
||||
# pin_names = self.replica_bitcell_array_inst.mod.replica_columns[self.rbls[0]].all_bitline_names
|
||||
# mirror = self.replica_col_insts[0].mirror
|
||||
# for (bl_name, pin_name) in zip(names, pin_names):
|
||||
# pin = inst.get_pin(pin_name)
|
||||
# if 'rbl_bl' in bl_name:
|
||||
# # if mirror != "MY":
|
||||
# # bl_name = bl_name.replace("rbl_bl","rbl_br")
|
||||
# self.add_layout_pin(text=bl_name,
|
||||
# layer=pin.layer,
|
||||
# offset=pin.ll().scale(1, 0),
|
||||
# width=pin.width(),
|
||||
# height=self.height)
|
||||
# elif 'rbl_br' in bl_name:
|
||||
# # if mirror != "MY":
|
||||
# # bl_name = bl_name.replace("rbl_br","rbl_bl")
|
||||
# self.add_layout_pin(text=bl_name,
|
||||
# layer=pin.layer,
|
||||
# offset=pin.ll().scale(1, 0) + vector(0,(pin_height + drc_width*2)),
|
||||
# width=pin.width(),
|
||||
# height=self.height - 2 *(pin_height + drc_width*2))
|
||||
return
|
||||
|
||||
@@ -8,20 +8,21 @@
|
||||
from openram import debug
|
||||
from openram.base import design
|
||||
from openram.tech import cell_properties as props
|
||||
|
||||
from openram import OPTS
|
||||
|
||||
class sky130_col_cap(design):
|
||||
|
||||
def __init__(self, version, name=""):
|
||||
def __init__(self, version, name="",left_rbl=[],right_rbl=[]):
|
||||
|
||||
if version == "colend":
|
||||
cell_name = "sky130_fd_bd_sram__sram_sp_colend"
|
||||
prop = props.col_cap_1port_bitcell
|
||||
elif version == "colenda":
|
||||
cell_name = "sky130_fd_bd_sram__sram_sp_colenda"
|
||||
prop = props.col_cap_1port_bitcell
|
||||
elif version == "colend_p_cent":
|
||||
cell_name = "sky130_fd_bd_sram__sram_sp_colend_p_cent"
|
||||
prop = props.col_cap_1port_strap_ground
|
||||
elif version == "colenda":
|
||||
cell_name = "sky130_fd_bd_sram__sram_sp_colenda"
|
||||
prop = props.col_cap_1port_bitcell
|
||||
elif version == "colenda_p_cent":
|
||||
cell_name = "sky130_fd_bd_sram__sram_sp_colenda_p_cent"
|
||||
prop = props.col_cap_1port_strap_ground
|
||||
@@ -32,5 +33,5 @@ class sky130_col_cap(design):
|
||||
cell_name = "sky130_fd_bd_sram__sram_sp_colenda_cent"
|
||||
prop = props.col_cap_1port_strap_power
|
||||
else:
|
||||
debug.error("Invalid type for col_end", -1)
|
||||
debug.error("Invalid type for col_end: {}".format(version), -1)
|
||||
super().__init__(name=name, cell_name=cell_name, prop=prop)
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
#!/usr/bin/env python3
|
||||
#!/usr/bin/env python3
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2023 Regents of the University of California
|
||||
@@ -9,247 +9,91 @@ from openram.base import geometry
|
||||
from openram.sram_factory import factory
|
||||
from openram.tech import layer
|
||||
from openram import OPTS
|
||||
from openram.modules.col_cap_array import col_cap_array
|
||||
from .sky130_bitcell_base_array import sky130_bitcell_base_array
|
||||
from openram.modules import pattern
|
||||
from math import ceil
|
||||
|
||||
class sky130_col_cap_array(sky130_bitcell_base_array):
|
||||
class sky130_col_cap_array(col_cap_array, sky130_bitcell_base_array):
|
||||
"""
|
||||
Generate a dummy row/column for the replica array.
|
||||
"""
|
||||
def __init__(self, rows, cols, location, column_offset=0, mirror=0, name=""):
|
||||
# Don't call the regular col-cap_array constructor since we don't want its constructor, just
|
||||
# some of it's useful member functions
|
||||
sky130_bitcell_base_array.__init__(self, rows=rows, cols=cols, column_offset=column_offset, name=name)
|
||||
self.mirror = mirror
|
||||
self.location = location
|
||||
self.rows = rows
|
||||
self.cols = cols
|
||||
self.create_netlist()
|
||||
if not OPTS.netlist_only:
|
||||
self.create_layout()
|
||||
|
||||
def create_netlist(self):
|
||||
""" Create and connect the netlist """
|
||||
# This module has no wordlines
|
||||
# self.create_all_wordline_names()
|
||||
# This module has no bitlines
|
||||
# self.create_all_bitline_names()
|
||||
self.add_modules()
|
||||
self.create_all_wordline_names()
|
||||
self.add_pins()
|
||||
self.create_instances()
|
||||
|
||||
def create_layout(self):
|
||||
|
||||
self.place_array("dummy_r{0}_c{1}", self.mirror)
|
||||
self.add_layout_pins()
|
||||
self.add_supply_pins()
|
||||
self.add_boundary()
|
||||
self.DRC_LVS()
|
||||
def __init__(self, rows, cols, column_offset=0, row_offset=0, mirror=0, location="", name="", left_rbl=[],right_rbl=[]):
|
||||
self.left_rbl = left_rbl
|
||||
self.right_rbl = right_rbl
|
||||
super().__init__(rows, cols, column_offset=column_offset, mirror=mirror, location=location, name=name, left_rbl=left_rbl, right_rbl=right_rbl)
|
||||
self.no_instances = False
|
||||
|
||||
def add_modules(self):
|
||||
""" Add the modules used in this design """
|
||||
if self.location == "top":
|
||||
self.colend1 = factory.create(module_type="col_cap", version="colend")
|
||||
self.colend1 = factory.create(module_type="col_cap", version="colend",left_rbl=self.left_rbl, right_rbl=self.right_rbl)
|
||||
self.colend2 = factory.create(module_type="col_cap", version="colend_p_cent")
|
||||
self.colend3 = factory.create(module_type="col_cap", version="colend_cent")
|
||||
elif self.location == "bottom":
|
||||
self.colend1 = factory.create(module_type="col_cap", version="colenda")
|
||||
self.colend1 = factory.create(module_type="col_cap", version="colenda",left_rbl=self.left_rbl, right_rbl=self.right_rbl)
|
||||
self.colend2 = factory.create(module_type="col_cap", version="colenda_p_cent")
|
||||
self.colend3 = factory.create(module_type="col_cap", version="colenda_cent")
|
||||
|
||||
self.cell = factory.create(module_type=OPTS.bitcell, version="opt1")
|
||||
|
||||
def create_instances(self):
|
||||
""" Create the module instances used in this design """
|
||||
self.cell_inst = {}
|
||||
self.array_layout = []
|
||||
bitline = 0
|
||||
for col in range((self.column_size * 2) - 1):
|
||||
row_layout = []
|
||||
name="rca_{0}_{1}".format(self.location, col)
|
||||
# Top/bottom cell are always dummy cells.
|
||||
# Regular array cells are replica cells (>left_rbl and <rows-right_rbl)
|
||||
# Replic bit specifies which other bit (in the full range (0,rows) to make a replica cell.
|
||||
pins = []
|
||||
if col % 4 == 0:
|
||||
row_layout.append(self.colend1)
|
||||
self.cell_inst[col]=self.add_inst(name=name, mod=self.colend1)
|
||||
pins.append("fake_bl_{}".format(bitline))
|
||||
pins.append("fake_br_{}".format(bitline))
|
||||
pins.append("vdd")
|
||||
pins.append("gnd")
|
||||
pins.append("vdd")
|
||||
pins.append("gnd")
|
||||
pins.append("gate")
|
||||
bitline += 1
|
||||
elif col % 4 == 1:
|
||||
row_layout.append(self.colend2)
|
||||
self.cell_inst[col]=self.add_inst(name=name, mod=self.colend3)
|
||||
pins.append("vdd")
|
||||
pins.append("vdd")
|
||||
pins.append("gnd")
|
||||
elif col % 4 == 2:
|
||||
row_layout.append(self.colend1)
|
||||
self.cell_inst[col]=self.add_inst(name=name, mod=self.colend1)
|
||||
pins.append("fake_bl_{}".format(bitline))
|
||||
pins.append("fake_br_{}".format(bitline))
|
||||
pins.append("vdd")
|
||||
pins.append("gnd")
|
||||
pins.append("vdd")
|
||||
pins.append("gnd")
|
||||
pins.append("gate")
|
||||
bitline += 1
|
||||
elif col % 4 ==3:
|
||||
row_layout.append(self.colend2)
|
||||
self.cell_inst[col]=self.add_inst(name=name, mod=self.colend2)
|
||||
pins.append("gnd")
|
||||
pins.append("vdd")
|
||||
pins.append("vnb")
|
||||
self.all_inst={}
|
||||
self.cell_inst={}
|
||||
|
||||
if self.location == "top":
|
||||
bit_row = [geometry.instance("02_colend", mod=self.colend1, is_bitcell=True, mirror="MY")] \
|
||||
+ [geometry.instance("03_strap_p", mod=self.colend3, is_bitcell=False)] \
|
||||
+ [geometry.instance("00_colend", mod=self.colend1, is_bitcell=True)] \
|
||||
+ [geometry.instance("01_strap_p_cent", mod=self.colend2, is_bitcell=False)]\
|
||||
|
||||
self.connect_inst(pins)
|
||||
|
||||
self.array_layout.append(row_layout)
|
||||
|
||||
def place_array(self, name_template, row_offset=0):
|
||||
xoffset = 0.0
|
||||
yoffset = 0.0
|
||||
|
||||
for col in range(len(self.insts)):
|
||||
inst = self.insts[col]
|
||||
if col % 4 == 0:
|
||||
inst.place(offset=[xoffset + inst.width, yoffset], mirror="MY")
|
||||
elif col % 4 == 1:
|
||||
inst.place(offset=[xoffset, yoffset])
|
||||
elif col % 4 == 2:
|
||||
inst.place(offset=[xoffset, yoffset])
|
||||
elif col % 4 ==3:
|
||||
inst.place(offset=[xoffset, yoffset])
|
||||
|
||||
xoffset += inst.width
|
||||
|
||||
self.width = max([x.rx() for x in self.insts])
|
||||
self.height = max([x.uy() for x in self.insts])
|
||||
|
||||
def add_pins(self):
|
||||
|
||||
for fake_bl in range(self.cols):
|
||||
self.add_pin("fake_bl_{}".format(fake_bl), "OUTPUT")
|
||||
self.add_pin("fake_br_{}".format(fake_bl), "OUTPUT")
|
||||
#self.add_pin("fake_wl", "INPUT")
|
||||
self.add_pin("vdd", "POWER")
|
||||
self.add_pin("gnd", "GROUND")
|
||||
self.add_pin("gate", "BIAS")
|
||||
elif self.location == "bottom":
|
||||
bit_row = [geometry.instance("02_colend", mod=self.colend1, is_bitcell=True, mirror="XY")] \
|
||||
+ [geometry.instance("03_strap_p", mod=self.colend3, is_bitcell=False, mirror="MX")] \
|
||||
+ [geometry.instance("00_colend", mod=self.colend1, is_bitcell=True, mirror="MX")] \
|
||||
+ [geometry.instance("01_strap_p_cent", mod=self.colend2, is_bitcell=False, mirror="MX")]\
|
||||
|
||||
|
||||
def add_layout_pins(self):
|
||||
""" Add the layout pins """
|
||||
# Add vdd/gnd via stacks
|
||||
for cols in range((self.column_size * 2) - 1):
|
||||
inst = self.cell_inst[cols]
|
||||
for pin_name in ["vdd", "gnd"]:
|
||||
for pin in inst.get_pins(pin_name):
|
||||
if inst.mod.cell_name == 'sky130_fd_bd_sram__sram_sp_colend' or 'sky130_fd_bd_sram__sram_sp_colenda':
|
||||
if inst.mirror == "MY":
|
||||
if pin_name == "vdd" and pin.layer == 'm1':
|
||||
self.add_layout_pin_rect_center(text="vdd",
|
||||
layer=pin.layer,
|
||||
offset=inst.lr(),
|
||||
width=pin.width(),
|
||||
height=pin.height())
|
||||
elif pin_name == "gnd" and pin.layer == 'm1':
|
||||
self.add_layout_pin_rect_center(text="gnd",
|
||||
layer=pin.layer,
|
||||
offset=inst.ll(),
|
||||
width=pin.width(),
|
||||
height=pin.height())
|
||||
else:
|
||||
if pin_name == "vdd" and pin.layer == 'm1':
|
||||
self.add_layout_pin_rect_center(text="vdd",
|
||||
layer=pin.layer,
|
||||
offset=inst.ll(),
|
||||
width=pin.width(),
|
||||
height=pin.height())
|
||||
elif pin_name == "gnd" and pin.layer == 'm1':
|
||||
self.add_layout_pin_rect_center(text="gnd",
|
||||
layer=pin.layer,
|
||||
offset=inst.lr(),
|
||||
width=pin.width(),
|
||||
height=pin.height())
|
||||
|
||||
bit_row = pattern.rotate_list(bit_row, self.column_offset * 2)
|
||||
bit_block = []
|
||||
pattern.append_row_to_block(bit_block, bit_row)
|
||||
self.pattern = pattern(self, "col_cap_array_" + self.location , bit_block, num_rows=self.row_size, num_cols=self.column_size, num_cores_x=ceil(self.column_size/2), num_cores_y=ceil(self.row_size/2), name_template="col_cap_array" + self.location + "_r{0}_c{1}")
|
||||
self.pattern.connect_array()
|
||||
|
||||
|
||||
def get_bitcell_pins(self, row, col):
|
||||
"""
|
||||
Creates a list of connections in the bitcell,
|
||||
indexed by column and row, for instance use in bitcell_array
|
||||
"""
|
||||
bitcell_pins = []
|
||||
for port in self.all_ports:
|
||||
bitcell_pins.extend([x for x in self.get_bitline_names(port) if x.endswith("_{0}".format(col))])
|
||||
bitcell_pins.append("vdd") # vdd
|
||||
bitcell_pins.append("gnd") # gnd
|
||||
bitcell_pins.append("vdd") # vpb
|
||||
bitcell_pins.append("gnd") # vnb
|
||||
bitcell_pins.append("gnd")# poly gate for parasitic tx
|
||||
#bitcell_pins.extend([x for x in self.all_wordline_names if x.endswith("_{0}".format(row))])
|
||||
|
||||
for col in range(len(self.insts)):
|
||||
|
||||
inst = self.insts[col]
|
||||
if col % 4 == 0:
|
||||
pin = self.cell_inst[col].get_pin("bl")
|
||||
text = "fake_bl_{}".format(int(col/2))
|
||||
self.add_layout_pin(text=text,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(1, 0),
|
||||
width=pin.width(),
|
||||
height=pin.height())
|
||||
|
||||
pin = self.cell_inst[col].get_pin("br")
|
||||
text = "fake_br_{}".format(int(col/2))
|
||||
self.add_layout_pin(text=text,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(1, 0),
|
||||
width=pin.width(),
|
||||
height=pin.height())
|
||||
|
||||
elif col % 4 == 2:
|
||||
pin = self.cell_inst[col].get_pin("bl")
|
||||
text = "fake_bl_{}".format(int(col/2))
|
||||
self.add_layout_pin(text=text,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(1, 0),
|
||||
width=pin.width(),
|
||||
height=pin.height())
|
||||
|
||||
pin = self.cell_inst[col].get_pin("br")
|
||||
text = "fake_br_{}".format(int(col/2))
|
||||
self.add_layout_pin(text=text,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(1, 0),
|
||||
width=pin.width(),
|
||||
height=pin.height())
|
||||
return
|
||||
return bitcell_pins
|
||||
|
||||
def add_supply_pins(self):
|
||||
for col in range(len(self.insts)):
|
||||
inst = self.cell_inst[col]
|
||||
def get_strap_pins(self, row, col):
|
||||
|
||||
strap_pins = []
|
||||
if col % 2 == 0 and col % 4 != 0:
|
||||
strap_pins.append("vdd") # vdd
|
||||
else:
|
||||
strap_pins.append("gnd") # gnd
|
||||
strap_pins.append("vdd") # vpb
|
||||
strap_pins.append("gnd") # vnb
|
||||
|
||||
return strap_pins
|
||||
|
||||
def create_layout(self):
|
||||
|
||||
if 'VPB' or 'vnb' in self.cell_inst[col].mod.pins:
|
||||
pin = inst.get_pin("vpb")
|
||||
self.objs.append(geometry.rectangle(layer["nwell"],
|
||||
pin.ll(),
|
||||
pin.width(),
|
||||
pin.height()))
|
||||
self.objs.append(geometry.label("vdd", layer["nwell"], pin.center()))
|
||||
self.place_array()
|
||||
self.add_layout_pins()
|
||||
|
||||
|
||||
if 'VNB' or 'vnb' in self.cell_inst[col].mod.pins:
|
||||
try:
|
||||
from openram.tech import layer_override
|
||||
if layer_override['VNB']:
|
||||
pin = inst.get_pin("vnb")
|
||||
self.objs.append(geometry.label("gnd", layer["pwellp"], pin.center()))
|
||||
self.objs.append(geometry.rectangle(layer["pwellp"],
|
||||
pin.ll(),
|
||||
pin.width(),
|
||||
pin.height()))
|
||||
except:
|
||||
pin = inst.get_pin("vnb")
|
||||
self.add_label("vdd", pin.layer, pin.center())
|
||||
|
||||
|
||||
|
||||
def create_all_wordline_names(self, row_size=None):
|
||||
if row_size == None:
|
||||
row_size = self.row_size
|
||||
|
||||
for row in range(row_size):
|
||||
for port in self.all_ports:
|
||||
self.wordline_names[port].append("wl_{0}_{1}".format(port, row))
|
||||
|
||||
self.all_wordline_names = [x for sl in zip(*self.wordline_names) for x in sl]
|
||||
self.add_boundary()
|
||||
self.DRC_LVS()
|
||||
|
||||
@@ -7,27 +7,22 @@
|
||||
|
||||
from openram import debug
|
||||
from openram.base import design
|
||||
from openram.base import get_libcell_size
|
||||
from openram.tech import layer, GDS
|
||||
from openram.tech import cell_properties as props
|
||||
|
||||
|
||||
class sky130_corner(design):
|
||||
|
||||
def __init__(self, location, name=""):
|
||||
super().__init__(name)
|
||||
|
||||
if location == "ul":
|
||||
self.name = "sky130_fd_bd_sram__sram_sp_corner"
|
||||
cell_name = "sky130_fd_bd_sram__sram_sp_corner"
|
||||
elif location == "ur":
|
||||
self.name = "sky130_fd_bd_sram__sram_sp_cornerb"
|
||||
cell_name = "sky130_fd_bd_sram__sram_sp_cornerb"
|
||||
elif location == "ll":
|
||||
self.name = "sky130_fd_bd_sram__sram_sp_cornera"
|
||||
cell_name = "sky130_fd_bd_sram__sram_sp_cornera"
|
||||
elif location == "lr":
|
||||
self.name = "sky130_fd_bd_sram__sram_sp_cornera"
|
||||
cell_name = "sky130_fd_bd_sram__sram_sp_cornera"
|
||||
else:
|
||||
debug.error("Invalid sky130_corner location", -1)
|
||||
design.__init__(self, name=self.name)
|
||||
(self.width, self.height) = get_libcell_size(self.name,
|
||||
GDS["unit"],
|
||||
layer["mem"])
|
||||
# pin_map = get_libcell_pins(pin_names, self.name, GDS["unit"])
|
||||
super().__init__(name=name, cell_name=cell_name, prop=props.col_cap_1port_strap_power)
|
||||
self.no_instances = True
|
||||
|
||||
|
||||
@@ -10,186 +10,61 @@ from openram.sram_factory import factory
|
||||
from openram.tech import layer
|
||||
from openram import OPTS
|
||||
from .sky130_bitcell_base_array import sky130_bitcell_base_array
|
||||
from openram.modules import dummy_array
|
||||
from openram.modules import pattern
|
||||
from math import ceil
|
||||
|
||||
class sky130_dummy_array(sky130_bitcell_base_array):
|
||||
class sky130_dummy_array(dummy_array, sky130_bitcell_base_array):
|
||||
"""
|
||||
Generate a dummy row/column for the replica array.
|
||||
"""
|
||||
def __init__(self, rows, cols, column_offset=0, row_offset=0 ,mirror=0, location="", name=""):
|
||||
|
||||
super().__init__(rows=rows, cols=cols, column_offset=column_offset, name=name)
|
||||
self.mirror = mirror
|
||||
|
||||
self.create_netlist()
|
||||
if not OPTS.netlist_only:
|
||||
self.create_layout()
|
||||
|
||||
def create_netlist(self):
|
||||
""" Create and connect the netlist """
|
||||
# This will create a default set of bitline/wordline names
|
||||
self.create_all_bitline_names()
|
||||
self.create_all_wordline_names()
|
||||
|
||||
self.add_modules()
|
||||
self.add_pins()
|
||||
self.create_instances()
|
||||
|
||||
def create_layout(self):
|
||||
self.place_array("dummy_r{0}_c{1}", self.mirror)
|
||||
|
||||
self.add_layout_pins()
|
||||
self.add_supply_pins()
|
||||
self.add_boundary()
|
||||
|
||||
self.DRC_LVS()
|
||||
|
||||
def add_modules(self):
|
||||
""" Add the modules used in this design """
|
||||
self.dummy_cell = factory.create(module_type=OPTS.dummy_bitcell, version="opt1")
|
||||
self.dummy_cell2 = factory.create(module_type=OPTS.dummy_bitcell, version="opt1a")
|
||||
self.dummy_cella = factory.create(module_type=OPTS.dummy_bitcell, version="opt1a")
|
||||
|
||||
self.strap = factory.create(module_type="internal", version="wlstrap")
|
||||
self.strap2 = factory.create(module_type="internal", version="wlstrap_p")
|
||||
self.strap3 = factory.create(module_type="internal", version="wlstrapa")
|
||||
self.strap4 = factory.create(module_type="internal", version="wlstrapa_p")
|
||||
self.strap_p = factory.create(module_type="internal", version="wlstrap_p")
|
||||
self.strapa = factory.create(module_type="internal", version="wlstrapa")
|
||||
self.strapa_p = factory.create(module_type="internal", version="wlstrapa_p")
|
||||
self.cell = factory.create(module_type=OPTS.bitcell, version="opt1")
|
||||
|
||||
def create_instances(self):
|
||||
""" Create the module instances used in this design """
|
||||
self.cell_inst = {}
|
||||
self.array_layout = []
|
||||
alternate_bitcell = (self.row_size + 1) % 2
|
||||
for row in range(0, self.row_size):
|
||||
# this code needs to use connect_array_raw() to make dummy columns correctly, but single port shouldn't need these since there are dedicated cap cells
|
||||
self.all_inst={}
|
||||
self.cell_inst={}
|
||||
|
||||
bit_row_opt1 = [geometry.instance("00_opt1", mod=self.dummy_cell, is_bitcell=True, mirror='MX')] \
|
||||
+ [geometry.instance("01_strap", mod=self.strap, is_bitcell=False, mirror='MX')]\
|
||||
+ [geometry.instance("02_opt1", mod=self.dummy_cell, is_bitcell=True, mirror='XY')] \
|
||||
+ [geometry.instance("03_strap_p", mod=self.strap_p, is_bitcell=False, mirror='MX')]
|
||||
|
||||
bit_row_opt1a = [geometry.instance("10_opt1a", mod=self.dummy_cella, is_bitcell=True, mirror='')] \
|
||||
+ [geometry.instance("11_strapa", mod=self.strapa, is_bitcell=False, mirror='')] \
|
||||
+ [geometry.instance("12_opt1a", mod=self.dummy_cella, is_bitcell=True, mirror='MY')] \
|
||||
+ [geometry.instance("13_strapa_p", mod=self.strapa_p, is_bitcell=False, mirror='')]
|
||||
|
||||
row_layout = []
|
||||
|
||||
alternate_strap = (self.row_size + 1) % 2
|
||||
for col in range(0, self.column_size):
|
||||
if alternate_bitcell == 1:
|
||||
row_layout.append(self.dummy_cell)
|
||||
self.cell_inst[row, col]=self.add_inst(name="row_{}_col_{}_bitcell".format(row, col),
|
||||
mod=self.dummy_cell)
|
||||
else:
|
||||
row_layout.append(self.dummy_cell2)
|
||||
self.cell_inst[row, col]=self.add_inst(name="row_{}_col_{}_bitcell".format(row, col),
|
||||
mod=self.dummy_cell2)
|
||||
self.connect_inst(self.get_bitcell_pins(row, col))
|
||||
if col != self.column_size - 1:
|
||||
if alternate_strap:
|
||||
if col % 2:
|
||||
name="row_{}_col_{}_wlstrap_p".format(row, col)
|
||||
row_layout.append(self.strap4)
|
||||
self.add_inst(name=name,
|
||||
mod=self.strap4)
|
||||
else:
|
||||
name="row_{}_col_{}_wlstrapa_p".format(row, col)
|
||||
row_layout.append(self.strap2)
|
||||
self.add_inst(name=name,
|
||||
mod=self.strap2)
|
||||
alternate_strap = 0
|
||||
else:
|
||||
if col % 2:
|
||||
name="row_{}_col_{}_wlstrap".format(row, col)
|
||||
row_layout.append(self.strap)
|
||||
self.add_inst(name=name,
|
||||
mod=self.strap)
|
||||
else:
|
||||
name="row_{}_col_{}_wlstrapa".format(row, col)
|
||||
row_layout.append(self.strap3)
|
||||
self.add_inst(name=name,
|
||||
mod=self.strap3)
|
||||
alternate_strap = 1
|
||||
|
||||
self.connect_inst(self.get_strap_pins(row, col, name))
|
||||
if alternate_bitcell == 0:
|
||||
alternate_bitcell = 1
|
||||
|
||||
bit_block = []
|
||||
if(self.row_offset % 2 == 0):
|
||||
next_row = 1
|
||||
else:
|
||||
next_row = 0
|
||||
|
||||
for i in range(self.row_size):
|
||||
if next_row == 0:
|
||||
pattern.append_row_to_block(bit_block, bit_row_opt1)
|
||||
next_row = 1
|
||||
else:
|
||||
alternate_bitcell = 0
|
||||
self.array_layout.append(row_layout)
|
||||
pattern.append_row_to_block(bit_block, bit_row_opt1a)
|
||||
next_row = 0
|
||||
|
||||
def add_pins(self):
|
||||
# bitline pins are not added because they are floating
|
||||
for bl in range(self.column_size):
|
||||
self.add_pin("bl_0_{}".format(bl))
|
||||
self.add_pin("br_0_{}".format(bl))
|
||||
for wl_name in self.get_wordline_names():
|
||||
self.add_pin(wl_name, "INPUT")
|
||||
self.add_pin("vdd", "POWER")
|
||||
self.add_pin("gnd", "GROUND")
|
||||
#self.add_pin("vpb", "BIAS")
|
||||
#Sself.add_pin("vnb", "BIAS")
|
||||
for row in bit_block:
|
||||
row = pattern.rotate_list(row, self.column_offset * 2)
|
||||
|
||||
def add_layout_pins(self):
|
||||
""" Add the layout pins """
|
||||
bitline_names = self.cell.get_all_bitline_names()
|
||||
for col in range(self.column_size):
|
||||
for port in self.all_ports:
|
||||
bl_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port])
|
||||
text = "bl_{0}_{1}".format(port, col)
|
||||
self.add_layout_pin(text=text,
|
||||
layer=bl_pin.layer,
|
||||
offset=bl_pin.ll().scale(1, 0),
|
||||
width=bl_pin.width(),
|
||||
height=self.height)
|
||||
br_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port + 1])
|
||||
text = "br_{0}_{1}".format(port, col)
|
||||
self.add_layout_pin(text=text,
|
||||
layer=br_pin.layer,
|
||||
offset=br_pin.ll().scale(1, 0),
|
||||
width=br_pin.width(),
|
||||
height=self.height)
|
||||
# self.add_rect(layer=bl_pin.layer,
|
||||
# offset=bl_pin.ll().scale(1, 0),
|
||||
# width=bl_pin.width(),
|
||||
# height=self.height)
|
||||
# self.add_rect(layer=br_pin.layer,
|
||||
# offset=br_pin.ll().scale(1, 0),
|
||||
# width=br_pin.width(),
|
||||
# height=self.height)
|
||||
|
||||
wl_names = self.cell.get_all_wl_names()
|
||||
for row in range(self.row_size):
|
||||
for port in self.all_ports:
|
||||
wl_pin = self.cell_inst[row, 0].get_pin(wl_names[port])
|
||||
self.add_layout_pin(text="wl_{0}_{1}".format(port, row),
|
||||
layer=wl_pin.layer,
|
||||
offset=wl_pin.ll().scale(0, 1),
|
||||
width=self.width,
|
||||
height=wl_pin.height())
|
||||
|
||||
# Copy a vdd/gnd layout pin from every cell
|
||||
for row in range(self.row_size):
|
||||
for col in range(self.column_size):
|
||||
inst = self.cell_inst[row, col]
|
||||
for pin_name in ["vdd", "gnd"]:
|
||||
self.copy_layout_pin(inst, pin_name)
|
||||
|
||||
def add_supply_pins(self):
|
||||
for row in range(self.row_size):
|
||||
for col in range(self.column_size):
|
||||
inst = self.cell_inst[row, col]
|
||||
if 'VPB' or 'vpb' in self.cell_inst[row, col].mod.pins:
|
||||
pin = inst.get_pin("vpb")
|
||||
self.objs.append(geometry.rectangle(layer["nwell"],
|
||||
pin.ll(),
|
||||
pin.width(),
|
||||
pin.height()))
|
||||
self.objs.append(geometry.label("vdd", layer["nwell"], pin.center()))
|
||||
|
||||
if 'VNB' or 'vnb' in self.cell_inst[row, col].mod.pins:
|
||||
try:
|
||||
from openram.tech import layer_override
|
||||
if layer_override['VNB']:
|
||||
pin = inst.get_pin("vnb")
|
||||
self.objs.append(geometry.label("gnd", layer["pwellp"], pin.center()))
|
||||
self.objs.append(geometry.rectangle(layer["pwellp"],
|
||||
pin.ll(),
|
||||
pin.width(),
|
||||
pin.height()))
|
||||
except:
|
||||
pin = inst.get_pin("vnb")
|
||||
self.add_label("vdd", pin.layer, pin.center())
|
||||
|
||||
def input_load(self):
|
||||
# FIXME: This appears to be old code from previous characterization. Needs to be updated.
|
||||
wl_wire = self.gen_wl_wire()
|
||||
return wl_wire.return_input_cap()
|
||||
self.pattern = pattern(self, "bitcell_array", bit_block, num_rows=self.row_size, num_cols=self.column_size, num_cores_x=ceil(self.column_size/2), num_cores_y=ceil(self.row_size/2), name_template="dummy_bit_r{0}_c{1}")
|
||||
self.pattern.connect_array()
|
||||
|
||||
@@ -21,9 +21,9 @@ class sky130_dummy_bitcell(bitcell_base):
|
||||
# Ignore the name argument
|
||||
|
||||
if version == "opt1":
|
||||
cell_name = "sky130_fd_bd_sram__openram_sp_cell_opt1_dummy"
|
||||
cell_name = "sky130_fd_bd_sram__openram_sp_cell_opt1_noblcon"
|
||||
elif version == "opt1a":
|
||||
cell_name = "sky130_fd_bd_sram__openram_sp_cell_opt1a_dummy"
|
||||
cell_name = "sky130_fd_bd_sram__openram_sp_cell_opt1a_noblcon"
|
||||
super().__init__(name, cell_name, prop=props.bitcell_1port)
|
||||
debug.info(2, "Create dummy bitcell")
|
||||
|
||||
|
||||
@@ -13,7 +13,7 @@ from openram.tech import drc
|
||||
from openram.tech import array_row_multiple
|
||||
from openram.tech import array_col_multiple
|
||||
from openram import OPTS
|
||||
from .replica_bitcell_array import replica_bitcell_array
|
||||
from openram.modules.replica_bitcell_array import replica_bitcell_array
|
||||
from .sky130_bitcell_base_array import sky130_bitcell_base_array
|
||||
|
||||
|
||||
@@ -26,390 +26,7 @@ class sky130_replica_bitcell_array(replica_bitcell_array, sky130_bitcell_base_ar
|
||||
Requires a regular bitcell array, replica bitcell, and dummy
|
||||
bitcell (Bl/BR disconnected).
|
||||
"""
|
||||
def __init__(self, rows, cols, rbl=None, left_rbl=None, right_rbl=None, name=""):
|
||||
total_ports = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports
|
||||
self.all_ports = list(range(total_ports))
|
||||
def __init__(self, rows=0, cols=0, rbl=None, left_rbl=None, right_rbl=None, column_offset=0, row_offset=0, name="",):
|
||||
debug.check((cols+ sum(rbl)) % 2==0, "must have an even number of cols including replica cols; you can add a spare col to fix this")
|
||||
super().__init__(rows, cols, rbl, left_rbl, right_rbl, column_offset, row_offset, name)
|
||||
|
||||
self.column_size = cols
|
||||
self.row_size = rows
|
||||
|
||||
# This is how many RBLs are in all the arrays
|
||||
if rbl:
|
||||
self.rbl = rbl
|
||||
else:
|
||||
self.rbl=[1, 1 if len(self.all_ports)>1 else 0]
|
||||
# This specifies which RBL to put on the left or right
|
||||
# by port number
|
||||
# This could be an empty list
|
||||
if left_rbl != None:
|
||||
self.left_rbl = left_rbl
|
||||
else:
|
||||
self.left_rbl = [0]
|
||||
# This could be an empty list
|
||||
if right_rbl != None:
|
||||
self.right_rbl = right_rbl
|
||||
else:
|
||||
self.right_rbl=[1] if len(self.all_ports) > 1 else []
|
||||
self.rbls = self.left_rbl + self.right_rbl
|
||||
|
||||
if ((self.column_size + self.rbl[0] + self.rbl[1]) % array_col_multiple != 0):
|
||||
debug.error("Invalid number of cols including rbl(s): {}. Total cols must be divisible by {}".format(self.column_size + self.rbl[0] + self.rbl[1], array_col_multiple), -1)
|
||||
|
||||
if ((self.row_size + self.rbl[0] + self.rbl[1]) % array_row_multiple != 0):
|
||||
debug.error("invalid number of rows including dummy row(s): {}. Total cols must be divisible by {}".format(self.row_size + self.rbl[0] + self.rbl[1], array_row_multiple), -15)
|
||||
|
||||
super().__init__(self.row_size, self.column_size, rbl, left_rbl, right_rbl, name)
|
||||
|
||||
def create_layout(self):
|
||||
# We will need unused wordlines grounded, so we need to know their layer
|
||||
# and create a space on the left and right for the vias to connect to ground
|
||||
pin = self.cell.get_pin(self.cell.get_all_wl_names()[0])
|
||||
pin_layer = pin.layer
|
||||
self.unused_pitch = 1.5 * getattr(self, "{}_pitch".format(pin_layer))
|
||||
self.unused_offset = vector(self.unused_pitch, 0)
|
||||
|
||||
# This is a bitcell x bitcell offset to scale
|
||||
self.bitcell_offset = vector(self.cell.width, self.cell.height)
|
||||
self.strap_offset = vector(self.replica_col_insts[0].mod.strap1.width, self.replica_col_insts[0].mod.strap1.height)
|
||||
self.col_end_offset = vector(self.dummy_row_insts[0].mod.colend1.width, self.dummy_row_insts[0].mod.colend1.height)
|
||||
self.row_end_offset = vector(self.dummy_col_insts[0].mod.rowend1.width, self.dummy_col_insts[0].mod.rowend1.height)
|
||||
|
||||
# Everything is computed with the main array at (self.unused_pitch, 0) to start
|
||||
self.bitcell_array_inst.place(offset=self.unused_offset)
|
||||
|
||||
self.add_replica_columns()
|
||||
|
||||
self.add_end_caps()
|
||||
|
||||
# Array was at (0, 0) but move everything so it is at the lower left
|
||||
self.offset_all_coordinates()
|
||||
|
||||
# Add extra width on the left and right for the unused WLs
|
||||
#self.width = self.dummy_col_insts[0].rx() + self.unused_offset[0]
|
||||
self.width = self.dummy_col_insts[1].rx()
|
||||
self.height = self.dummy_col_insts[0].uy()
|
||||
|
||||
self.add_layout_pins()
|
||||
|
||||
self.route_unused_wordlines()
|
||||
|
||||
self.add_boundary()
|
||||
|
||||
self.DRC_LVS()
|
||||
|
||||
def add_pins(self):
|
||||
super().add_pins()
|
||||
|
||||
def add_replica_columns(self):
|
||||
""" Add replica columns on left and right of array """
|
||||
|
||||
# Grow from left to right, toward the array
|
||||
for bit, port in enumerate(self.left_rbl):
|
||||
offset = self.bitcell_array_inst.ll() \
|
||||
- vector(0, self.col_cap_bottom.height) \
|
||||
- vector(0, self.dummy_row.height) \
|
||||
- vector(self.replica_columns[0].width, 0)
|
||||
self.replica_col_insts[bit].place(offset + vector(0, self.replica_col_insts[bit].height), mirror="MX")
|
||||
|
||||
# Grow to the right of the bitcell array, array outward
|
||||
for bit, port in enumerate(self.right_rbl):
|
||||
offset = self.bitcell_array_inst.lr() \
|
||||
+ self.bitcell_offset.scale(bit, -self.rbl[0] - (self.col_end_offset.y / self.cell.height)) \
|
||||
+ self.strap_offset.scale(bit, -self.rbl[0] - 1)
|
||||
self.replica_col_insts[self.rbl[0] + bit].place(offset)
|
||||
|
||||
# Replica dummy rows
|
||||
# Add the dummy rows even if we aren't adding the replica column to this bitcell array
|
||||
# These grow up, toward the array
|
||||
for bit in range(self.rbl[0]):
|
||||
dummy_offset = self.bitcell_offset.scale(0, -self.rbl[0] + bit + (-self.rbl[0] + bit) % 2) + self.unused_offset
|
||||
self.dummy_row_replica_insts[bit].place(offset=dummy_offset,
|
||||
mirror="MX" if (-self.rbl[0] + bit) % 2 else "R0")
|
||||
# These grow up, away from the array
|
||||
for bit in range(self.rbl[1]):
|
||||
dummy_offset = self.bitcell_offset.scale(0, bit + bit % 2) + self.bitcell_array_inst.ul()
|
||||
self.dummy_row_replica_insts[self.rbl[0] + bit].place(offset=dummy_offset,
|
||||
mirror="MX" if bit % 2 else "R0")
|
||||
|
||||
def add_end_caps(self):
|
||||
""" Add dummy cells or end caps around the array """
|
||||
|
||||
dummy_row_offset = self.bitcell_offset.scale(0, self.rbl[1]) + self.bitcell_array_inst.ul()
|
||||
self.dummy_row_insts[1].place(offset=dummy_row_offset)
|
||||
|
||||
dummy_row_offset = self.bitcell_offset.scale(0, -self.rbl[0] - (self.col_end_offset.y / self.cell.height)) + self.unused_offset
|
||||
self.dummy_row_insts[0].place(offset=dummy_row_offset + vector(0, self.dummy_row_insts[0].height), mirror="MX")
|
||||
|
||||
# Far left dummy col
|
||||
# Shifted down by the number of left RBLs even if we aren't adding replica column to this bitcell array
|
||||
dummy_col_offset = self.bitcell_offset.scale(len(self.right_rbl) * (1 + self.strap_offset.x / self.cell.width), -self.rbl[0] - (self.col_end_offset.y / self.cell.height)) - vector(self.replica_col_insts[0].width, 0) + self.unused_offset
|
||||
self.dummy_col_insts[0].place(offset=dummy_col_offset, mirror="MY")
|
||||
|
||||
# Far right dummy col
|
||||
# Shifted down by the number of left RBLs even if we aren't adding replica column to this bitcell array
|
||||
dummy_col_offset = self.bitcell_offset.scale(len(self.right_rbl) * (1 + self.strap_offset.x / self.cell.width), -self.rbl[0] - (self.col_end_offset.y / self.cell.height)) + self.bitcell_array_inst.lr()
|
||||
self.dummy_col_insts[1].place(offset=dummy_col_offset)
|
||||
|
||||
def route_unused_wordlines(self):
|
||||
""" Connect the unused RBL and dummy wordlines to gnd """
|
||||
return
|
||||
# This grounds all the dummy row word lines
|
||||
for inst in self.dummy_row_insts:
|
||||
for wl_name in self.col_cap.get_wordline_names():
|
||||
self.ground_pin(inst, wl_name)
|
||||
|
||||
# Ground the unused replica wordlines
|
||||
for (names, inst) in zip(self.rbl_wordline_names, self.dummy_row_replica_insts):
|
||||
for (wl_name, pin_name) in zip(names, self.dummy_row.get_wordline_names()):
|
||||
if wl_name in self.gnd_wordline_names:
|
||||
self.ground_pin(inst, pin_name)
|
||||
|
||||
def add_layout_pins(self):
|
||||
""" Add the layout pins """
|
||||
|
||||
for row_end in self.dummy_col_insts:
|
||||
row_end = row_end.mod
|
||||
for (rba_wl_name, wl_name) in zip(self.get_all_wordline_names(), row_end.get_wordline_names()):
|
||||
pin = row_end.get_pin(wl_name)
|
||||
self.add_layout_pin(text=rba_wl_name,
|
||||
layer=pin.layer,
|
||||
offset=vector(0,pin.ll().scale(0, 1)[1]),
|
||||
#width=self.width,
|
||||
width=pin.width(),
|
||||
height=pin.height())
|
||||
|
||||
pin_height = (round_to_grid(drc["minarea_m3"] / round_to_grid(sqrt(drc["minarea_m3"]))) + drc["{0}_to_{0}".format('m3')])
|
||||
drc_width = drc["{0}_to_{0}".format('m3')]
|
||||
|
||||
# vdd/gnd are only connected in the perimeter cells
|
||||
# replica column should only have a vdd/gnd in the dummy cell on top/bottom
|
||||
supply_insts = self.dummy_row_insts + self.replica_col_insts
|
||||
|
||||
for pin_name in self.supplies:
|
||||
for supply_inst in supply_insts:
|
||||
vdd_alternate = 0
|
||||
gnd_alternate = 0
|
||||
for cell_inst in supply_inst.mod.insts:
|
||||
inst = cell_inst.mod
|
||||
for pin in inst.get_pins(pin_name):
|
||||
if pin.name == 'vdd':
|
||||
if vdd_alternate:
|
||||
connection_offset = 0.035
|
||||
vdd_alternate = 0
|
||||
else:
|
||||
connection_offset = -0.035
|
||||
vdd_alternate = 1
|
||||
connection_width = drc["minwidth_{}".format('m1')]
|
||||
track_offset = 1
|
||||
elif pin.name == 'gnd':
|
||||
if gnd_alternate:
|
||||
connection_offset = 0.035
|
||||
gnd_alternate = 0
|
||||
else:
|
||||
connection_offset = -0.035
|
||||
gnd_alternate = 1
|
||||
connection_width = drc["minwidth_{}".format('m1')]
|
||||
track_offset = 4
|
||||
pin_width = round_to_grid(sqrt(drc["minarea_m3"]))
|
||||
pin_height = round_to_grid(drc["minarea_m3"] / pin_width)
|
||||
if inst.cell_name == 'sky130_fd_bd_sram__sram_sp_colend_p_cent' or inst.cell_name == 'sky130_fd_bd_sram__sram_sp_colenda_p_cent' or inst.cell_name == 'sky130_fd_bd_sram__sram_sp_colend_cent' or inst.cell_name == 'sky130_fd_bd_sram__sram_sp_colenda_cent' or 'corner' in inst.cell_name:
|
||||
if 'dummy_row' in supply_inst.name and supply_inst.mirror == 'MX':
|
||||
pin_center = vector(pin.center()[0], -1 * track_offset * (pin_height + drc_width*2))
|
||||
self.add_segment_center(pin.layer, pin_center+supply_inst.ll()+cell_inst.ll()+vector(connection_offset,0), vector((pin_center+supply_inst.ll()+cell_inst.ll())[0] + connection_offset, 0), connection_width)
|
||||
elif 'dummy_row' in supply_inst.name:
|
||||
pin_center = vector(pin.center()[0],inst.height + 1 * track_offset* (pin_height + drc_width*2))
|
||||
self.add_segment_center(pin.layer, pin_center+supply_inst.ll()+cell_inst.ll()+vector(connection_offset,0), vector((pin_center+supply_inst.ll()+cell_inst.ll())[0] + connection_offset, self.height), connection_width)
|
||||
elif 'replica_col' in supply_inst.name and cell_inst.mirror == 'MX':
|
||||
pin_center = vector(pin.center()[0], -1 * track_offset* (pin_height + drc_width*2))
|
||||
self.add_segment_center(pin.layer, pin_center+supply_inst.ll()+cell_inst.ll()+vector(connection_offset,0), vector((pin_center+supply_inst.ll()+cell_inst.ll())[0] + connection_offset, 0), connection_width)
|
||||
elif 'replica_col' in supply_inst.name:
|
||||
pin_center = vector(pin.center()[0],inst.height + 1 * track_offset * (pin_height + drc_width*2))
|
||||
self.add_segment_center(pin.layer, pin_center+supply_inst.ll()+cell_inst.ll()+vector(connection_offset,0), vector((pin_center+supply_inst.ll()+cell_inst.ll())[0] + connection_offset,self.height), connection_width)
|
||||
self.add_via_stack_center(from_layer=pin.layer,
|
||||
to_layer='m2',
|
||||
offset=pin_center+supply_inst.ll()+cell_inst.ll() + vector(connection_offset,0))
|
||||
|
||||
|
||||
# add well contacts to perimeter cells
|
||||
for pin_name in ['vpb', 'vnb']:
|
||||
for supply_inst in supply_insts:
|
||||
vnb_alternate = 0
|
||||
vpb_alternate = 0
|
||||
for cell_inst in supply_inst.mod.insts:
|
||||
|
||||
inst = cell_inst.mod
|
||||
for pin in inst.get_pins(pin_name):
|
||||
if pin.name == 'vpb':
|
||||
if vpb_alternate:
|
||||
connection_offset = 0.01
|
||||
vpb_alternate = 0
|
||||
else:
|
||||
connection_offset = 0.02
|
||||
vpb_alternate = 1
|
||||
connection_width = drc["minwidth_{}".format('m1')]
|
||||
track_offset = 2
|
||||
elif pin.name == 'vnb':
|
||||
if vnb_alternate:
|
||||
connection_offset = -0.01
|
||||
vnb_alternate = 0
|
||||
else:
|
||||
connection_offset = -0.02
|
||||
vnb_alternate = 1
|
||||
connection_width = drc["minwidth_{}".format('m1')]
|
||||
track_offset = 3
|
||||
if inst.cell_name == 'sky130_fd_bd_sram__sram_sp_colend_p_cent' or inst.cell_name == 'sky130_fd_bd_sram__sram_sp_colenda_p_cent' or inst.cell_name == 'sky130_fd_bd_sram__sram_sp_colend_cent' or inst.cell_name == 'sky130_fd_bd_sram__sram_sp_colenda_cent':
|
||||
if 'dummy_row' in supply_inst.name and supply_inst.mirror == 'MX':
|
||||
pin_center = vector(pin.center()[0], -1 * track_offset * (pin_height + drc_width*2))
|
||||
self.add_segment_center(pin.layer, pin_center+supply_inst.ll()+cell_inst.ll()+vector(connection_offset,0), vector((pin_center+supply_inst.ll()+cell_inst.ll())[0] + connection_offset, 0), connection_width)
|
||||
elif 'dummy_row' in supply_inst.name:
|
||||
pin_center = vector(pin.center()[0],inst.height + 1 * track_offset* (pin_height + drc_width*2))
|
||||
self.add_segment_center(pin.layer, pin_center+supply_inst.ll()+cell_inst.ll()+vector(connection_offset,0), vector((pin_center+supply_inst.ll()+cell_inst.ll())[0] + connection_offset, self.height), connection_width)
|
||||
elif 'replica_col' in supply_inst.name and cell_inst.mirror == 'MX':
|
||||
pin_center = vector(pin.center()[0], -1 * track_offset* (pin_height + drc_width*2))
|
||||
self.add_segment_center(pin.layer, pin_center+supply_inst.ll()+cell_inst.ll()+vector(connection_offset,0), vector((pin_center+supply_inst.ll()+cell_inst.ll())[0] + connection_offset, 0), connection_width)
|
||||
elif 'replica_col' in supply_inst.name:
|
||||
pin_center = vector(pin.center()[0],inst.height + 1 * track_offset * (pin_height + drc_width*2))
|
||||
self.add_segment_center(pin.layer, pin_center+supply_inst.ll()+cell_inst.ll()+vector(connection_offset,0), vector((pin_center+supply_inst.ll()+cell_inst.ll())[0] + connection_offset,self.height), connection_width)
|
||||
self.add_via_stack_center(from_layer=pin.layer,
|
||||
to_layer='m2',
|
||||
offset=pin_center+supply_inst.ll()+cell_inst.ll() + vector(connection_offset,0))
|
||||
|
||||
min_area = drc["minarea_{}".format('m3')]
|
||||
for track,supply, offset in zip(range(1,5),['vdd','vdd','gnd','gnd'],[min_area * 6,min_area * 6, 0, 0]):
|
||||
y_offset = track * (pin_height + drc_width*2)
|
||||
self.add_segment_center('m2', vector(0,-y_offset), vector(self.width, -y_offset), drc["minwidth_{}".format('m2')])
|
||||
self.add_segment_center('m2', vector(0,self.height + y_offset), vector(self.width, self.height + y_offset), drc["minwidth_{}".format('m2')])
|
||||
self.add_power_pin(name=supply,
|
||||
loc=vector(round_to_grid(sqrt(min_area))/2 + offset, -y_offset),
|
||||
start_layer='m2')
|
||||
self.add_power_pin(name=supply,
|
||||
loc=vector(round_to_grid(sqrt(min_area))/2 + offset, self.height + y_offset),
|
||||
start_layer='m2')
|
||||
self.add_power_pin(name=supply,
|
||||
loc=vector(self.width - round_to_grid(sqrt(min_area))/2 - offset, -y_offset),
|
||||
start_layer='m2')
|
||||
self.add_power_pin(name=supply,
|
||||
loc=vector(self.width - round_to_grid(sqrt(min_area))/2 - offset, self.height + y_offset),
|
||||
start_layer='m2')
|
||||
|
||||
self.offset_all_coordinates()
|
||||
self.height = self.height + self.dummy_col_insts[0].lr().y * 2
|
||||
|
||||
for pin_name in self.all_bitline_names:
|
||||
pin_list = self.bitcell_array_inst.get_pins(pin_name)
|
||||
for pin in pin_list:
|
||||
if 'bl' in pin.name:
|
||||
self.add_layout_pin(text=pin_name,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(1, 0),
|
||||
width=pin.width(),
|
||||
height=self.height)
|
||||
elif 'br' in pin_name:
|
||||
self.add_layout_pin(text=pin_name,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(1, 0) + vector(0,pin_height + drc_width*2),
|
||||
width=pin.width(),
|
||||
height=self.height - 2 *(pin_height + drc_width*2))
|
||||
# Replica bitlines
|
||||
if len(self.rbls) > 0:
|
||||
for (names, inst) in zip(self.rbl_bitline_names, self.replica_col_insts):
|
||||
pin_names = self.replica_columns[self.rbls[0]].all_bitline_names
|
||||
mirror = self.replica_col_insts[0].mirror
|
||||
for (bl_name, pin_name) in zip(names, pin_names):
|
||||
pin = inst.get_pin(pin_name)
|
||||
if 'rbl_bl' in bl_name:
|
||||
# if mirror != "MY":
|
||||
# bl_name = bl_name.replace("rbl_bl","rbl_br")
|
||||
self.add_layout_pin(text=bl_name,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(1, 0),
|
||||
width=pin.width(),
|
||||
height=self.height)
|
||||
elif 'rbl_br' in bl_name:
|
||||
# if mirror != "MY":
|
||||
# bl_name = bl_name.replace("rbl_br","rbl_bl")
|
||||
self.add_layout_pin(text=bl_name,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(1, 0) + vector(0,(pin_height + drc_width*2)),
|
||||
width=pin.width(),
|
||||
height=self.height - 2 *(pin_height + drc_width*2))
|
||||
return
|
||||
|
||||
def add_wordline_pins(self):
|
||||
|
||||
# Wordlines to ground
|
||||
self.gnd_wordline_names = []
|
||||
|
||||
for port in self.all_ports:
|
||||
for bit in self.all_ports:
|
||||
self.rbl_wordline_names[port].append("rbl_wl_{0}_{1}".format(port, bit))
|
||||
if bit != port:
|
||||
self.gnd_wordline_names.append("rbl_wl_{0}_{1}".format(port, bit))
|
||||
|
||||
self.all_rbl_wordline_names = [x for sl in self.rbl_wordline_names for x in sl]
|
||||
|
||||
self.wordline_names = self.bitcell_array.wordline_names
|
||||
self.all_wordline_names = self.bitcell_array.all_wordline_names
|
||||
|
||||
# All wordlines including dummy and RBL
|
||||
self.replica_array_wordline_names = []
|
||||
#self.replica_array_wordline_names.extend(["gnd"] * len(self.col_cap_top.get_wordline_names()))
|
||||
for bit in range(self.rbl[0]):
|
||||
self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[bit]])
|
||||
self.replica_array_wordline_names.extend(self.all_wordline_names)
|
||||
for bit in range(self.rbl[1]):
|
||||
self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[self.rbl[0] + bit]])
|
||||
#self.replica_array_wordline_names.extend(["gnd"] * len(self.col_cap_top.get_wordline_names()))
|
||||
|
||||
for port in range(self.rbl[0]):
|
||||
self.add_pin(self.rbl_wordline_names[port][port], "INPUT")
|
||||
self.add_pin_list(self.all_wordline_names, "INPUT")
|
||||
for port in range(self.rbl[0], self.rbl[0] + self.rbl[1]):
|
||||
self.add_pin(self.rbl_wordline_names[port][port], "INPUT")
|
||||
|
||||
def create_instances(self):
|
||||
""" Create the module instances used in this design """
|
||||
self.supplies = ["vdd", "gnd"]
|
||||
|
||||
# Used for names/dimensions only
|
||||
# self.cell = factory.create(module_type=OPTS.bitcell)
|
||||
|
||||
# Main array
|
||||
self.bitcell_array_inst=self.add_inst(name="bitcell_array",
|
||||
mod=self.bitcell_array)
|
||||
self.connect_inst(self.all_bitline_names + self.all_wordline_names + self.supplies)
|
||||
# Replica columns
|
||||
self.replica_col_insts = []
|
||||
for port in self.all_ports:
|
||||
if port in self.rbls:
|
||||
self.replica_col_insts.append(self.add_inst(name="replica_col_{}".format(port),
|
||||
mod=self.replica_columns[port]))
|
||||
self.connect_inst(self.rbl_bitline_names[port] + self.replica_array_wordline_names + self.supplies + ["gnd"] + ["gnd"])
|
||||
else:
|
||||
self.replica_col_insts.append(None)
|
||||
|
||||
# Dummy rows under the bitcell array (connected with with the replica cell wl)
|
||||
self.dummy_row_replica_insts = []
|
||||
# Note, this is the number of left and right even if we aren't adding the columns to this bitcell array!
|
||||
for port in self.all_ports:
|
||||
self.dummy_row_replica_insts.append(self.add_inst(name="dummy_row_{}".format(port),
|
||||
mod=self.dummy_row))
|
||||
self.connect_inst(self.all_bitline_names + [x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[port]] + self.supplies)
|
||||
|
||||
# Top/bottom dummy rows or col caps
|
||||
self.dummy_row_insts = []
|
||||
self.dummy_row_insts.append(self.add_inst(name="dummy_row_bot",
|
||||
mod=self.col_cap_bottom))
|
||||
self.connect_inst(self.all_bitline_names + self.supplies + ["gnd"])
|
||||
self.dummy_row_insts.append(self.add_inst(name="dummy_row_top",
|
||||
mod=self.col_cap_top))
|
||||
self.connect_inst(self.all_bitline_names + self.supplies + ["gnd"])
|
||||
|
||||
# Left/right Dummy columns
|
||||
self.dummy_col_insts = []
|
||||
self.dummy_col_insts.append(self.add_inst(name="dummy_col_left",
|
||||
mod=self.row_cap_left))
|
||||
self.connect_inst(["dummy_left_" + bl for bl in self.row_cap_left.all_bitline_names] + ["gnd"] + self.replica_array_wordline_names + ["gnd"] + self.supplies)
|
||||
self.dummy_col_insts.append(self.add_inst(name="dummy_col_right",
|
||||
mod=self.row_cap_right))
|
||||
self.connect_inst(["dummy_right_" + bl for bl in self.row_cap_right.all_bitline_names] + ["gnd"] + self.replica_array_wordline_names + ["gnd"] + self.supplies)
|
||||
|
||||
@@ -11,9 +11,9 @@ from openram.sram_factory import factory
|
||||
from openram.tech import layer
|
||||
from openram import OPTS
|
||||
from .sky130_bitcell_base_array import sky130_bitcell_base_array
|
||||
|
||||
|
||||
class sky130_replica_column(sky130_bitcell_base_array):
|
||||
from openram.modules import pattern
|
||||
from openram.modules import replica_column
|
||||
class sky130_replica_column(replica_column, sky130_bitcell_base_array):
|
||||
"""
|
||||
Generate a replica bitline column for the replica array.
|
||||
Rows is the total number of rows i the main array.
|
||||
@@ -23,75 +23,7 @@ class sky130_replica_column(sky130_bitcell_base_array):
|
||||
"""
|
||||
|
||||
def __init__(self, name, rows, rbl, replica_bit, column_offset=0):
|
||||
# Used for pin names and properties
|
||||
self.cell = factory.create(module_type=OPTS.bitcell)
|
||||
# Row size is the number of rows with word lines
|
||||
self.row_size = sum(rbl) + rows
|
||||
# Start of regular word line rows
|
||||
self.row_start = rbl[0] + 1
|
||||
# End of regular word line rows
|
||||
self.row_end = self.row_start + rows
|
||||
if not self.cell.end_caps:
|
||||
self.row_size += 2
|
||||
super().__init__(rows=self.row_size, cols=1, column_offset=column_offset, name=name)
|
||||
|
||||
self.rows = rows
|
||||
self.left_rbl = rbl[0]
|
||||
self.right_rbl = rbl[1]
|
||||
self.replica_bit = replica_bit
|
||||
# left, right, regular rows plus top/bottom dummy cells
|
||||
|
||||
self.total_size = self.left_rbl + rows + self.right_rbl + 2
|
||||
self.column_offset = column_offset
|
||||
|
||||
if self.rows % 2 == 0:
|
||||
debug.error("Invalid number of rows {}. Number of rows must be even to connect to col ends".format(self.rows), -1)
|
||||
if self.column_offset % 2 == 0:
|
||||
debug.error("Invalid column_offset {}. Column offset must be odd to connect to col ends".format(self.rows), -1)
|
||||
debug.check(replica_bit != 0 and replica_bit != rows,
|
||||
"Replica bit cannot be the dummy row.")
|
||||
debug.check(replica_bit <= self.left_rbl or replica_bit >= self.total_size - self.right_rbl - 1,
|
||||
"Replica bit cannot be in the regular array.")
|
||||
# if OPTS.tech_name == "sky130":
|
||||
# debug.check(rows % 2 == 0 and (self.left_rbl + 1) % 2 == 0,
|
||||
# "sky130 currently requires rows to be even and to start with X mirroring"
|
||||
# + " (left_rbl must be even) for LVS.")
|
||||
# commented out to support odd row counts while testing opc
|
||||
|
||||
self.create_netlist()
|
||||
if not OPTS.netlist_only:
|
||||
self.create_layout()
|
||||
|
||||
def create_netlist(self):
|
||||
self.add_modules()
|
||||
self.add_pins()
|
||||
self.create_instances()
|
||||
|
||||
def create_layout(self):
|
||||
self.place_instances()
|
||||
|
||||
self.width = max([x.rx() for x in self.insts])
|
||||
self.height = max([x.uy() for x in self.insts])
|
||||
|
||||
self.add_layout_pins()
|
||||
|
||||
self.add_boundary()
|
||||
self.DRC_LVS()
|
||||
|
||||
def add_pins(self):
|
||||
|
||||
self.create_all_bitline_names()
|
||||
#self.create_all_wordline_names(self.row_size+2)
|
||||
# +2 to add fake wl pins for colends
|
||||
self.create_all_wordline_names(self.row_size+1, 1)
|
||||
self.add_pin_list(self.all_bitline_names, "OUTPUT")
|
||||
self.add_pin_list(self.all_wordline_names, "INPUT")
|
||||
|
||||
self.add_pin("vdd", "POWER")
|
||||
self.add_pin("gnd", "GROUND")
|
||||
|
||||
self.add_pin("top_gate", "INPUT")
|
||||
self.add_pin("bot_gate", "INPUT")
|
||||
super().__init__(name=name, rows=rows, rbl=rbl, replica_bit=replica_bit, column_offset=column_offset)
|
||||
|
||||
def add_modules(self):
|
||||
self.replica_cell = factory.create(module_type="replica_bitcell_1port", version="opt1")
|
||||
@@ -99,172 +31,65 @@ class sky130_replica_column(sky130_bitcell_base_array):
|
||||
self.replica_cell2 = factory.create(module_type="replica_bitcell_1port", version="opt1a")
|
||||
|
||||
self.dummy_cell = factory.create(module_type="dummy_bitcell_1port", version="opt1")
|
||||
self.dummy_cell2 = factory.create(module_type="dummy_bitcell_1port", version="opt1")
|
||||
|
||||
self.strap1 = factory.create(module_type="internal", version="wlstrap")
|
||||
self.strap2 = factory.create(module_type="internal", version="wlstrap_p")
|
||||
self.strap3 = factory.create(module_type="internal", version="wlstrapa_p")
|
||||
|
||||
self.colend = factory.create(module_type="col_cap", version="colend")
|
||||
self.edge_cell = self.colend
|
||||
self.colenda = factory.create(module_type="col_cap", version="colenda")
|
||||
self.colend_p_cent = factory.create(module_type="col_cap", version="colend_p_cent")
|
||||
self.colenda_p_cent = factory.create(module_type="col_cap", version="colenda_p_cent")
|
||||
self.dummy_cell2 = factory.create(module_type="dummy_bitcell_1port", version="opt1a")
|
||||
|
||||
self.strap = factory.create(module_type="internal", version="wlstrap")
|
||||
self.strap_p = factory.create(module_type="internal", version="wlstrap_p")
|
||||
self.strapa = factory.create(module_type="internal", version="wlstrapa")
|
||||
self.strapa_p = factory.create(module_type="internal", version="wlstrapa_p")
|
||||
|
||||
def create_instances(self):
|
||||
self.cell_inst = {}
|
||||
self.array_layout = []
|
||||
alternate_bitcell = (self.rows + 1) % 2
|
||||
""" Create the module instances used in this design """
|
||||
self.all_inst={}
|
||||
self.cell_inst={}
|
||||
|
||||
replica_row_opt1 = [geometry.instance("rep_00_opt1", mod=self.replica_cell, is_bitcell=True, mirror='XY')] \
|
||||
+ [geometry.instance("rep_01_strap_p", mod=self.strap_p, is_bitcell=False, mirror='MX')]\
|
||||
+ [geometry.instance("rep_02_opt1", mod=self.replica_cell, is_bitcell=True, mirror='MX')] \
|
||||
+ [geometry.instance("rep_03_strap", mod=self.strap, is_bitcell=False, mirror='MX')]
|
||||
|
||||
replica_row_opt1a = [geometry.instance("rep_10_opt1a", mod=self.replica_cell2, is_bitcell=True, mirror='MY')] \
|
||||
+ [geometry.instance("rep_11_strap_p", mod=self.strap_p, is_bitcell=False)] \
|
||||
+ [geometry.instance("rep_12_opt1a", mod=self.replica_cell2, is_bitcell=True)] \
|
||||
+ [geometry.instance("rep_13_strapaa", mod=self.strapa, is_bitcell=False)]
|
||||
|
||||
dummy_row_opt1 = [geometry.instance("dummy_00_opt1", mod=self.dummy_cell, is_bitcell=True, mirror='XY')] \
|
||||
+ [geometry.instance("dummy_01_strap_p", mod=self.strap_p, is_bitcell=False, mirror='MX')]\
|
||||
+ [geometry.instance("dummy_02_opt1", mod=self.dummy_cell, is_bitcell=True, mirror='MX')] \
|
||||
+ [geometry.instance("dummy_03_strap", mod=self.strap, is_bitcell=False, mirror='MX')]
|
||||
|
||||
dummy_row_opt1a = [geometry.instance("dummy_10_opt1a", mod=self.dummy_cell2, is_bitcell=True, mirror='MY')] \
|
||||
+ [geometry.instance("dummy_11_strap_p", mod=self.strap_p, is_bitcell=False)] \
|
||||
+ [geometry.instance("dummy_12_opt1a", mod=self.dummy_cell2, is_bitcell=True)] \
|
||||
+ [geometry.instance("dummy_13_strapa", mod=self.strapa, is_bitcell=False)]
|
||||
|
||||
bit_block = []
|
||||
if self.column_offset % 2 == 1:
|
||||
replica_row_opt1 = replica_row_opt1[0:2]
|
||||
replica_row_opt1a = replica_row_opt1a[0:2]
|
||||
dummy_row_opt1 = dummy_row_opt1[0:2]
|
||||
dummy_row_opt1a = dummy_row_opt1a[0:2]
|
||||
else:
|
||||
replica_row_opt1 = replica_row_opt1[2:4]
|
||||
replica_row_opt1a = replica_row_opt1a[2:4]
|
||||
dummy_row_opt1 = dummy_row_opt1[2:4]
|
||||
dummy_row_opt1a = dummy_row_opt1a[2:4]
|
||||
current_row = self.row_start
|
||||
for row in range(self.total_size):
|
||||
row_layout = []
|
||||
name="rbc_{0}".format(row)
|
||||
# Top/bottom cell are always dummy cells.
|
||||
# Regular array cells are replica cells (>left_rbl and <rows-right_rbl)
|
||||
# Replic bit specifies which other bit (in the full range (0,rows) to make a replica cell.
|
||||
if (row > self.left_rbl and row < self.total_size - 1 or row == self.replica_bit):
|
||||
|
||||
if alternate_bitcell == 0:
|
||||
row_layout.append(self.replica_cell)
|
||||
self.cell_inst[row]=self.add_inst(name=name, mod=self.replica_cell)
|
||||
self.connect_inst(self.get_bitcell_pins(row, 0))
|
||||
row_layout.append(self.strap2)
|
||||
self.add_inst(name=name + "_strap_p", mod=self.strap2)
|
||||
self.connect_inst(self.get_strap_pins(row, 0, name + "_strap_p"))
|
||||
alternate_bitcell = 1
|
||||
|
||||
# Regular array cells are replica cells
|
||||
# Replic bit specifies which other bit (in the full range (0,total_size) to make a replica cell.
|
||||
# All other cells are dummies
|
||||
if (row == self.replica_bit) or (row >= self.row_start and row < self.row_end):
|
||||
if current_row % 2 == 0:
|
||||
pattern.append_row_to_block(bit_block, replica_row_opt1)
|
||||
else:
|
||||
row_layout.append(self.replica_cell2)
|
||||
self.cell_inst[row]=self.add_inst(name=name, mod=self.replica_cell2)
|
||||
self.connect_inst(self.get_bitcell_pins(row, 0))
|
||||
row_layout.append(self.strap3)
|
||||
self.add_inst(name=name + "_strap", mod=self.strap3)
|
||||
self.connect_inst(self.get_strap_pins(row, 0))
|
||||
alternate_bitcell = 0
|
||||
|
||||
elif (row == 0):
|
||||
row_layout.append(self.colend)
|
||||
self.cell_inst[row]=self.add_inst(name=name, mod=self.colend)
|
||||
self.connect_inst(self.get_col_cap_pins(row, 0))
|
||||
row_layout.append(self.colend_p_cent)
|
||||
self.add_inst(name=name + "_cap", mod=self.colend_p_cent)
|
||||
self.connect_inst(self.get_col_cap_p_pins(row, 0))
|
||||
elif (row == self.total_size - 1):
|
||||
row_layout.append(self.colenda)
|
||||
self.cell_inst[row]=self.add_inst(name=name, mod=self.colenda)
|
||||
self.connect_inst(self.get_col_cap_pins(row, 0))
|
||||
row_layout.append(self.colenda_p_cent)
|
||||
self.add_inst(name=name + "_cap", mod=self.colenda_p_cent)
|
||||
self.connect_inst(self.get_col_cap_p_pins(row, 0))
|
||||
|
||||
self.array_layout.append(row_layout)
|
||||
|
||||
def place_instances(self, name_template="", row_offset=0):
|
||||
col_offset = self.column_offset
|
||||
yoffset = 0.0
|
||||
|
||||
for row in range(row_offset, len(self.array_layout) + row_offset):
|
||||
xoffset = 0.0
|
||||
for col in range(col_offset, len(self.array_layout[row]) + col_offset):
|
||||
self.place_inst = self.insts[(col - col_offset) + (row - row_offset) * len(self.array_layout[row - row_offset])]
|
||||
if row == row_offset or row == (len(self.array_layout) + row_offset -1):
|
||||
if row == row_offset:
|
||||
self.place_inst.place(offset=[xoffset, yoffset + self.colend.height], mirror="MX")
|
||||
else:
|
||||
self.place_inst.place(offset=[xoffset, yoffset])
|
||||
|
||||
elif col % 2 == 0:
|
||||
if row % 2 == 0:
|
||||
self.place_inst.place(offset=[xoffset, yoffset + self.place_inst.height], mirror="MX")
|
||||
else:
|
||||
self.place_inst.place(offset=[xoffset, yoffset])
|
||||
else:
|
||||
if row % 2 == 0:
|
||||
self.place_inst.place(offset=[xoffset + self.place_inst.width, yoffset + self.place_inst.height], mirror="XY")
|
||||
else:
|
||||
self.place_inst.place(offset=[xoffset + self.place_inst.width, yoffset], mirror="MY")
|
||||
|
||||
xoffset += self.place_inst.width
|
||||
if row == row_offset:
|
||||
yoffset += self.colend.height
|
||||
pattern.append_row_to_block(bit_block, replica_row_opt1a)
|
||||
else:
|
||||
yoffset += self.place_inst.height
|
||||
if current_row % 2 == 0:
|
||||
pattern.append_row_to_block(bit_block, dummy_row_opt1)
|
||||
else:
|
||||
pattern.append_row_to_block(bit_block, dummy_row_opt1a)
|
||||
current_row += 1
|
||||
self.pattern = pattern(self, "replica_column", bit_block, num_rows=self.total_size, num_cols=len(replica_row_opt1), name_template="rbc_r{0}_c{1}")
|
||||
self.pattern.connect_array_raw()
|
||||
|
||||
self.width = max([x.rx() for x in self.insts])
|
||||
self.height = max([x.uy() for x in self.insts])
|
||||
|
||||
def add_layout_pins(self):
|
||||
""" Add the layout pins """
|
||||
for port in self.all_ports:
|
||||
bl_pin = self.cell_inst[2].get_pin(self.cell.get_bl_name(port))
|
||||
self.add_layout_pin(text="bl_{0}_{1}".format(port, 0),
|
||||
layer=bl_pin.layer,
|
||||
offset=bl_pin.ll().scale(1, 0),
|
||||
width=bl_pin.width(),
|
||||
height=self.height)
|
||||
bl_pin = self.cell_inst[2].get_pin(self.cell.get_br_name(port))
|
||||
self.add_layout_pin(text="br_{0}_{1}".format(port, 0),
|
||||
layer=bl_pin.layer,
|
||||
offset=bl_pin.ll().scale(1, 0),
|
||||
width=bl_pin.width(),
|
||||
height=self.height)
|
||||
|
||||
row_range_max = self.total_size - 1
|
||||
row_range_min = 1
|
||||
|
||||
for port in self.all_ports:
|
||||
for row in range(row_range_min, row_range_max):
|
||||
wl_pin = self.cell_inst[row].get_pin(self.cell.get_wl_name(port))
|
||||
self.add_layout_pin(text="wl_{0}_{1}".format(port, row_range_max-row),
|
||||
layer=wl_pin.layer,
|
||||
offset=wl_pin.ll().scale(0, 1),
|
||||
width=self.width,
|
||||
height=wl_pin.height())
|
||||
|
||||
# for colend in [self.cell_inst[0], self.cell_inst[self.row_size]]:
|
||||
# inst = self.cell_inst[row]
|
||||
# for pin_name in ["top_gate", "bot_gate"]:
|
||||
# pin = inst.get_pin("gate")
|
||||
# self.add_layout_pin(text=pin_name,
|
||||
# layer=pin.layer,
|
||||
# offset=pin.ll(),
|
||||
# width=pin.width(),
|
||||
# height=pin.height())
|
||||
|
||||
for row in range(self.row_size + 2):
|
||||
inst = self.cell_inst[row]
|
||||
# add only 1 label per col
|
||||
for pin_name in ["vdd", "gnd"]:
|
||||
self.copy_layout_pin(inst, pin_name)
|
||||
#if row == 2:
|
||||
if 'VPB' or 'vpb' in self.cell_inst[row].mod.pins:
|
||||
pin = inst.get_pin("vpb")
|
||||
self.objs.append(geometry.rectangle(layer["nwell"],
|
||||
pin.ll(),
|
||||
pin.width(),
|
||||
pin.height()))
|
||||
self.objs.append(geometry.label("vdd", layer["nwell"], pin.center()))
|
||||
|
||||
if 'VNB' or 'vnb' in self.cell_inst[row].mod.pins:
|
||||
try:
|
||||
from openram.tech import layer_override
|
||||
if layer_override['VNB']:
|
||||
pin = inst.get_pin("vnb")
|
||||
self.add_label("gnd", pin.layer, pin.center())
|
||||
self.objs.append(geometry.rectangle(layer["pwellp"],
|
||||
pin.ll(),
|
||||
pin.width(),
|
||||
pin.height()))
|
||||
self.objs.append(geometry.label("gnd", layer["pwellp"], pin.center()))
|
||||
|
||||
|
||||
except:
|
||||
pin = inst.get_pin("vnb")
|
||||
self.add_label("gnd", pin.layer, pin.center())
|
||||
|
||||
def exclude_all_but_replica(self):
|
||||
"""
|
||||
Excludes all bits except the replica cell (self.replica_bit).
|
||||
"""
|
||||
for row, cell in self.cell_inst.items():
|
||||
if row != self.replica_bit:
|
||||
self.graph_inst_exclude.add(cell)
|
||||
|
||||
@@ -5,140 +5,98 @@
|
||||
# All rights reserved.
|
||||
#
|
||||
|
||||
from openram.base import geometry
|
||||
from openram.sram_factory import factory
|
||||
from openram import OPTS
|
||||
from .sky130_bitcell_base_array import sky130_bitcell_base_array
|
||||
from openram.modules.row_cap_array import row_cap_array
|
||||
from openram.modules.pattern import pattern
|
||||
from math import ceil
|
||||
|
||||
|
||||
class sky130_row_cap_array(sky130_bitcell_base_array):
|
||||
class sky130_row_cap_array(row_cap_array, sky130_bitcell_base_array):
|
||||
"""
|
||||
Generate a dummy row/column for the replica array.
|
||||
"""
|
||||
def __init__(self, rows, cols, column_offset=0, mirror=0, name=""):
|
||||
# Don't call the regular col-cap_array constructor since we don't want its constructor, just
|
||||
# some of it's useful member functions
|
||||
sky130_bitcell_base_array.__init__(self, rows=rows, cols=cols, column_offset=column_offset, name=name)
|
||||
self.rows = rows
|
||||
self.cols = cols
|
||||
self.column_offset = column_offset
|
||||
def __init__(self, rows, cols, column_offset=0, row_offset=0, mirror=0, location="", name=""):
|
||||
super().__init__(rows, cols, column_offset=column_offset, location=location, name=name)
|
||||
self.mirror = mirror
|
||||
self.create_netlist()
|
||||
if not OPTS.netlist_only:
|
||||
self.create_layout()
|
||||
|
||||
def create_netlist(self):
|
||||
""" Create and connect the netlist """
|
||||
self.create_all_wordline_names()
|
||||
# This module has no bitlines
|
||||
# self.create_all_bitline_names()
|
||||
|
||||
self.add_modules()
|
||||
self.add_pins()
|
||||
self.create_instances()
|
||||
|
||||
def create_layout(self):
|
||||
|
||||
self.place_array("dummy_r{0}_c{1}", self.mirror)
|
||||
self.add_layout_pins()
|
||||
|
||||
self.width = max([x.rx() for x in self.insts])
|
||||
self.height = max([x.uy() for x in self.insts])
|
||||
|
||||
self.add_boundary()
|
||||
self.DRC_LVS()
|
||||
|
||||
self.location = location
|
||||
def add_modules(self):
|
||||
""" Add the modules used in this design """
|
||||
if self.column_offset == 0:
|
||||
if self.location == "left":
|
||||
self.top_corner = factory.create(module_type="corner", location="ul")
|
||||
self.bottom_corner =factory.create(module_type="corner", location="ll")
|
||||
self.rowend1 = factory.create(module_type="row_cap", version="rowend_replica")
|
||||
self.rowend2 = factory.create(module_type="row_cap", version="rowenda_replica")
|
||||
#self.rowend1 = factory.create(module_type="row_cap", version="rowend_replica")
|
||||
#self.rowend2 = factory.create(module_type="row_cap", version="rowenda_replica")
|
||||
|
||||
else:
|
||||
self.top_corner = factory.create(module_type="corner", location="ur")
|
||||
self.bottom_corner = factory.create(module_type="corner", location="lr")
|
||||
|
||||
self.rowend1 = factory.create(module_type="row_cap", version="rowend")
|
||||
self.rowend2 = factory.create(module_type="row_cap", version="rowenda")
|
||||
|
||||
#self.rowend1 = factory.create(module_type="row_cap", version="rowend")
|
||||
#self.rowend2 = factory.create(module_type="row_cap", version="rowenda")
|
||||
self.rowend = factory.create(module_type="row_cap", version="rowend")
|
||||
self.rowenda = factory.create(module_type="row_cap", version="rowenda")
|
||||
self.cell = factory.create(module_type=OPTS.bitcell, version="opt1")
|
||||
|
||||
def create_instances(self):
|
||||
""" Create the module instances used in this design """
|
||||
self.cell_inst = {}
|
||||
self.array_layout = []
|
||||
alternate_bitcell = (self.rows + 1) % 2
|
||||
for row in range(self.rows + 2):
|
||||
row_layout = []
|
||||
name="rca_{0}".format(row)
|
||||
# Top/bottom cell are always dummy cells.
|
||||
# Regular array cells are replica cells (>left_rbl and <rows-right_rbl)
|
||||
# Replic bit specifies which other bit (in the full range (0,rows) to make a replica cell.
|
||||
self.all_inst={}
|
||||
self.cell_inst={}
|
||||
|
||||
bit_block = []
|
||||
|
||||
if self.location == "left":
|
||||
top_corner = geometry.instance("row_cap_top_corner", mod=self.top_corner, is_bitcell=False, mirror="MY")
|
||||
bottom_corner = geometry.instance("row_cap_bottom_corner", mod=self.bottom_corner, is_bitcell=False, mirror="XY")
|
||||
rowend = geometry.instance("row_cap_rowend", mod=self.rowend, is_bitcell=True, mirror="XY")
|
||||
rowenda = geometry.instance("row_cap_rowenda", mod=self.rowenda, is_bitcell=True, mirror="MY")
|
||||
elif self.location == "right":
|
||||
top_corner = geometry.instance("row_cap_top_corner", mod=self.top_corner, is_bitcell=False)
|
||||
bottom_corner = geometry.instance("row_cap_bottom_corner", mod=self.bottom_corner, is_bitcell=False, mirror="MX")
|
||||
rowend = geometry.instance("row_cap_rowend", mod=self.rowend, is_bitcell=True, mirror="MX")
|
||||
rowenda = geometry.instance("row_cap_rowenda", mod=self.rowenda, is_bitcell=True)
|
||||
|
||||
if (row < self.rows + 1 and row > 0):
|
||||
pattern.append_row_to_block(bit_block, [bottom_corner])
|
||||
for row in range(1, self.row_size-1):
|
||||
if row % 2 == 1:
|
||||
pattern.append_row_to_block(bit_block, [rowenda])
|
||||
|
||||
if alternate_bitcell == 0:
|
||||
row_layout.append(self.rowend1)
|
||||
self.cell_inst[row]=self.add_inst(name=name, mod=self.rowend1)
|
||||
self.connect_inst(["wl_0_{}".format(row - 1), "vdd"])
|
||||
alternate_bitcell = 1
|
||||
|
||||
else:
|
||||
row_layout.append(self.rowend2)
|
||||
self.cell_inst[row] = self.add_inst(name=name, mod=self.rowend2)
|
||||
self.connect_inst(["wl_0_{}".format(row - 1), "vdd"])
|
||||
alternate_bitcell = 0
|
||||
|
||||
elif (row == 0):
|
||||
row_layout.append(self.bottom_corner)
|
||||
self.cell_inst[row]=self.add_inst(name=name, mod=self.bottom_corner)
|
||||
self.connect_inst(self.get_corner_pins())
|
||||
|
||||
elif (row == self.rows + 1):
|
||||
row_layout.append(self.top_corner)
|
||||
self.cell_inst[row]=self.add_inst(name=name, mod=self.top_corner)
|
||||
self.connect_inst(self.get_corner_pins())
|
||||
|
||||
self.array_layout.append(row_layout)
|
||||
|
||||
def place_array(self, name_template, row_offset=0):
|
||||
xoffset = 0.0
|
||||
yoffset = 0.0
|
||||
for row in range(len(self.insts)):
|
||||
inst = self.insts[row]
|
||||
if row == 0:
|
||||
inst.place(offset=[xoffset, yoffset + inst.height], mirror="MX")
|
||||
elif row == len(self.insts)-1:
|
||||
inst.place(offset=[xoffset, yoffset])
|
||||
else:
|
||||
if row % 2 ==0:
|
||||
inst.place(offset=[xoffset, yoffset + inst.height], mirror="MX")
|
||||
else:
|
||||
inst.place(offset=[xoffset, yoffset])
|
||||
yoffset += inst.height
|
||||
pattern.append_row_to_block(bit_block, [rowend])
|
||||
|
||||
def add_pins(self):
|
||||
for row in range(self.rows + 2):
|
||||
for port in self.all_ports:
|
||||
self.add_pin("wl_{}_{}".format(port, row), "OUTPUT")
|
||||
self.add_pin("vdd", "POWER")
|
||||
self.add_pin("gnd", "GROUND")
|
||||
pattern.append_row_to_block(bit_block, [top_corner])
|
||||
self.pattern = pattern(self, "row_cap_array_" + self.location, bit_block, num_rows=self.row_size, num_cols=self.column_size, num_cores_x=ceil(self.column_size/2), num_cores_y=ceil(self.row_size/2), name_template="row_cap_array" + self.location + "_r{0}_c{1}")
|
||||
self.pattern.connect_array_raw()
|
||||
|
||||
|
||||
def get_bitcell_pins(self, row, col):
|
||||
"""
|
||||
Creates a list of connections in the bitcell,
|
||||
indexed by column and row, for instance use in bitcell_array
|
||||
"""
|
||||
|
||||
def add_layout_pins(self):
|
||||
""" Add the layout pins """
|
||||
for row in range(0, self.rows + 1):
|
||||
if row > 0 and row < self.rows + 1:
|
||||
wl_pin = self.cell_inst[row].get_pin("wl")
|
||||
self.add_layout_pin(text="wl_0_{0}".format(row -1),
|
||||
layer=wl_pin.layer,
|
||||
offset=wl_pin.ll().scale(0, 1),
|
||||
width=self.width,
|
||||
height=wl_pin.height())
|
||||
bitcell_pins = []
|
||||
bitcell_pins.append("vdd") # vdd
|
||||
bitcell_pins.extend([x for x in self.all_wordline_names if x.endswith("_{0}".format(row))])
|
||||
|
||||
# Add vdd/gnd via stacks
|
||||
for row in range(1, self.rows):
|
||||
inst = self.cell_inst[row]
|
||||
for pin_name in ["vdd", "gnd"]:
|
||||
for pin in inst.get_pins(pin_name):
|
||||
self.copy_layout_pin(inst, pin_name)
|
||||
return bitcell_pins
|
||||
|
||||
def get_strap_pins(self, row, col):
|
||||
|
||||
strap_pins = []
|
||||
|
||||
strap_pins.append("vdd") # vdd
|
||||
strap_pins.append("vdd") # vpb
|
||||
strap_pins.append("gnd") # vnb
|
||||
|
||||
return strap_pins
|
||||
|
||||
|
||||
def create_layout(self):
|
||||
|
||||
self.place_array()
|
||||
self.add_layout_pins()
|
||||
|
||||
self.add_boundary()
|
||||
self.DRC_LVS()
|
||||
|
||||
|
||||
@@ -5,837 +5,15 @@
|
||||
# All rights reserved.
|
||||
#
|
||||
|
||||
import sys
|
||||
from openram import OPTS
|
||||
|
||||
import os
|
||||
from openram import drc as d
|
||||
import os
|
||||
dir_path = os.path.dirname(os.path.realpath(__file__))
|
||||
|
||||
"""
|
||||
File containing the process technology parameters for Skywater 130nm.
|
||||
"""
|
||||
sys.path.append("{}/{}".format(dir_path,'tech_configs'))
|
||||
|
||||
###################################################
|
||||
# Custom modules
|
||||
###################################################
|
||||
|
||||
# This uses the default classes to instantiate module from
|
||||
# '$OPENRAM_HOME/compiler/modules'.
|
||||
# Using tech_modules['cellname'] you can override each class by providing a custom
|
||||
# implementation in '$OPENRAM_TECHDIR/modules/'
|
||||
# For example: tech_modules["contact"] = "contact_freepdk45"
|
||||
tech_modules = d.module_type()
|
||||
|
||||
# These modules have been hand designed and provided in this repository.
|
||||
tech_modules["nand2_dec"] = "nand2_dec"
|
||||
tech_modules["nand3_dec"] = "nand3_dec"
|
||||
tech_modules["nand4_dec"] = "nand4_dec"
|
||||
|
||||
# Override default OpenRAM modules to sky130 modules
|
||||
# These are for single port and dual port as a list,
|
||||
# or for both if there is no list,
|
||||
# or only applicable to one if there is no list.
|
||||
tech_modules["bitcell_1port"] = "sky130_bitcell"
|
||||
tech_modules["replica_bitcell_1port"] = "sky130_replica_bitcell"
|
||||
tech_modules["dummy_bitcell_1port"] = "sky130_dummy_bitcell"
|
||||
|
||||
tech_modules["replica_bitcell_2port"] = "replica_bitcell_2port"
|
||||
tech_modules["dummy_bitcell_2port"] = "dummy_bitcell_2port"
|
||||
tech_modules["bitcell_2port"] = "bitcell_2port"
|
||||
|
||||
tech_modules["bitcell_array"] = ["sky130_bitcell_array", "bitcell_array"]
|
||||
tech_modules["replica_bitcell_array"] = ["sky130_replica_bitcell_array", "replica_bitcell_array"]
|
||||
tech_modules["capped_replica_bitcell_array"] = ["sky130_capped_replica_bitcell_array", "capped_replica_bitcell_array"]
|
||||
tech_modules["dummy_array"] = ["sky130_dummy_array", "dummy_array"]
|
||||
|
||||
tech_modules["replica_column"] = ["sky130_replica_column", "replica_column"]
|
||||
|
||||
tech_modules["col_cap_array"] = ["sky130_col_cap_array", "col_cap_array"]
|
||||
tech_modules["col_cap"] = ["sky130_col_cap", "col_cap_bitcell_2port"]
|
||||
tech_modules["corner"] = ["sky130_corner", None]
|
||||
tech_modules["internal"] = ["sky130_internal", None]
|
||||
tech_modules["row_cap_array"] = ["sky130_row_cap_array", "row_cap_array"]
|
||||
tech_modules["row_cap"] = ["sky130_row_cap", "row_cap_bitcell_2port"]
|
||||
|
||||
# These modules are auto-generated from the nand decoders above and are not
|
||||
# found in this.
|
||||
tech_modules["buf_dec"] = "pbuf_dec"
|
||||
tech_modules["inv_dec"] = "pinv_dec"
|
||||
tech_modules["and2_dec"] = "and2_dec"
|
||||
tech_modules["and3_dec"] = "and3_dec"
|
||||
tech_modules["and4_dec"] = "and4_dec"
|
||||
|
||||
###################################################
|
||||
# Custom cell properties
|
||||
###################################################
|
||||
cell_properties = d.cell_properties()
|
||||
|
||||
cell_properties.bitcell_power_pin_directions = ("H", "H")
|
||||
|
||||
cell_properties.bitcell_1port.mirror.x = True
|
||||
cell_properties.bitcell_1port.mirror.y = True
|
||||
cell_properties.bitcell_1port.end_caps = True
|
||||
cell_properties.bitcell_1port.boundary_layer = "mem"
|
||||
cell_properties.bitcell_1port.port_order = ['bl', 'br', 'gnd', 'vdd', 'vpb', 'vnb', 'wl']
|
||||
cell_properties.bitcell_1port.port_types = ["OUTPUT", "OUTPUT", "GROUND", "POWER", "BIAS", "BIAS", "INPUT"]
|
||||
cell_properties.bitcell_1port.port_map = {'bl': 'BL',
|
||||
'br': 'BR',
|
||||
'wl': 'WL',
|
||||
'vdd': 'VPWR',
|
||||
'vnb': 'VNB',
|
||||
'vpb': 'VPB',
|
||||
'gnd': 'VGND'}
|
||||
|
||||
cell_properties.bitcell_1port.wl_layer = "m2"
|
||||
cell_properties.bitcell_1port.bl_layer = "m1"
|
||||
cell_properties.bitcell_1port.vdd_layer = "m1"
|
||||
cell_properties.bitcell_1port.vdd_dir = "V"
|
||||
cell_properties.bitcell_1port.gnd_layer = "m2"
|
||||
cell_properties.bitcell_1port.gnd_dir = "H"
|
||||
|
||||
cell_properties.bitcell_2port.mirror.x = True
|
||||
cell_properties.bitcell_2port.mirror.y = True
|
||||
cell_properties.bitcell_2port.end_caps = True
|
||||
cell_properties.bitcell_2port.port_order = ['bl0', 'br0', 'bl1', 'br1', 'wl0', 'wl1', 'vdd', 'gnd']
|
||||
cell_properties.bitcell_2port.port_map = {'bl0': 'BL0',
|
||||
'br0': 'BR0',
|
||||
'bl1': 'BL1',
|
||||
'br1': 'BR1',
|
||||
'wl0': 'WL0',
|
||||
'wl1': 'WL1',
|
||||
'vdd': 'VDD',
|
||||
'gnd': 'GND'}
|
||||
cell_properties.bitcell_1port.wl_layer = "m2"
|
||||
cell_properties.bitcell_1port.vdd_layer = "m2"
|
||||
cell_properties.bitcell_1port.vdd_dir = "H"
|
||||
cell_properties.bitcell_1port.gnd_layer = "m2"
|
||||
cell_properties.bitcell_1port.gnd_dir = "H"
|
||||
cell_properties.bitcell_2port.wl_layer = "m2"
|
||||
cell_properties.bitcell_2port.vdd_layer = "m1"
|
||||
cell_properties.bitcell_2port.vdd_dir = "H"
|
||||
cell_properties.bitcell_2port.gnd_layer = "m2"
|
||||
cell_properties.bitcell_2port.gnd_dir = "H"
|
||||
|
||||
cell_properties.col_cap_1port_bitcell = d.cell(['bl', 'br', 'vdd', 'gnd', 'vpb', 'vnb', 'gate'],
|
||||
['INPUT', 'INPUT','POWER', 'GROUND', 'BIAS', 'BIAS', 'INPUT'],
|
||||
{'bl': 'bl',
|
||||
'br': 'br',
|
||||
'vdd': 'vdd',
|
||||
'gnd': 'gnd',
|
||||
'vnb': 'vnb',
|
||||
'vpb': 'vpb',
|
||||
'gate': 'gate'})
|
||||
cell_properties.col_cap_1port_bitcell.boundary_layer = "mem"
|
||||
|
||||
cell_properties.col_cap_1port_strap_power = d.cell(['vdd', 'vpb', 'vnb'],
|
||||
['POWER', 'BIAS', 'BIAS'],
|
||||
{'vnb': 'VNB',
|
||||
'vpb': 'VPB',
|
||||
'vdd': 'VPWR'})
|
||||
cell_properties.col_cap_1port_strap_power.boundary_layer = "mem"
|
||||
|
||||
cell_properties.col_cap_1port_strap_ground = d.cell(['gnd', 'vpb', 'vnb'],
|
||||
['GROUND', 'BIAS', 'BIAS'],
|
||||
{'vnb': 'VNB',
|
||||
'vpb': 'VPB',
|
||||
'gnd': 'VGND'})
|
||||
cell_properties.col_cap_1port_strap_ground.boundary_layer = "mem"
|
||||
|
||||
cell_properties.row_cap_1port_cell = d.cell(['vdd', 'wl'],
|
||||
['POWER', 'INPUT'],
|
||||
{'wl': 'WL',
|
||||
'vdd': 'VPWR'})
|
||||
cell_properties.row_cap_1port_cell.boundary_layer = "mem"
|
||||
|
||||
cell_properties.col_cap_2port.port_order = ['bl0', 'br0', 'bl1', 'br1', 'vdd']
|
||||
cell_properties.col_cap_2port.port_map = {'bl0': 'BL0',
|
||||
'br0': 'BR0',
|
||||
'bl1': 'BL1',
|
||||
'br1': 'BR1',
|
||||
'vdd': 'VDD'}
|
||||
|
||||
cell_properties.row_cap_2port.port_order = ['wl0', 'wl1', 'gnd']
|
||||
cell_properties.row_cap_2port.port_map = {'wl0': 'WL0',
|
||||
'wl1': 'WL1',
|
||||
'gnd': 'GND'}
|
||||
|
||||
|
||||
cell_properties.ptx.bin_spice_models = True
|
||||
cell_properties.ptx.model_is_subckt = True
|
||||
|
||||
cell_properties.pgate.add_implants = True
|
||||
|
||||
cell_properties.use_strap = True
|
||||
cell_properties.strap_module = "internal"
|
||||
cell_properties.strap_version = "wlstrap"
|
||||
|
||||
cell_properties.dff.port_order = ['D', 'Q', 'clk', 'vdd', 'gnd']
|
||||
cell_properties.dff.port_map = {'D': 'D',
|
||||
'Q': 'Q',
|
||||
'clk': 'CLK',
|
||||
'vdd': 'VDD',
|
||||
'gnd': 'GND'}
|
||||
|
||||
cell_properties.nand2_dec.port_order = ['A', 'B', 'Z', 'vdd', 'gnd']
|
||||
cell_properties.nand2_dec.port_map = {'A': 'A',
|
||||
'B': 'B',
|
||||
'Z': 'Z',
|
||||
'vdd': 'VDD',
|
||||
'gnd': 'GND'}
|
||||
|
||||
cell_properties.nand3_dec.port_order = ['A', 'B', 'C', 'Z', 'vdd', 'gnd']
|
||||
cell_properties.nand3_dec.port_map = {'A': 'A',
|
||||
'B': 'B',
|
||||
'C': 'C',
|
||||
'Z': 'Z',
|
||||
'vdd': 'VDD',
|
||||
'gnd': 'GND'}
|
||||
|
||||
cell_properties.nand4_dec.port_order = ['A', 'B', 'C', 'D', 'Z', 'vdd', 'gnd']
|
||||
cell_properties.nand4_dec.port_map = {'A': 'A',
|
||||
'B': 'B',
|
||||
'C': 'C',
|
||||
'D': 'D',
|
||||
'Z': 'Z',
|
||||
'vdd': 'VDD',
|
||||
'gnd': 'GND'}
|
||||
|
||||
cell_properties.sense_amp.port_order = ['bl', 'br', 'dout', 'en', 'vdd', 'gnd']
|
||||
cell_properties.sense_amp.port_map = {'bl': 'BL',
|
||||
'br': 'BR',
|
||||
'dout': 'DOUT',
|
||||
'en': 'EN',
|
||||
'vdd': 'VDD',
|
||||
'gnd': 'GND'}
|
||||
|
||||
cell_properties.write_driver.port_order = ['din', 'bl', 'br', 'en', 'vdd', 'gnd']
|
||||
cell_properties.write_driver.port_map = {'din': 'DIN',
|
||||
'bl': 'BL',
|
||||
'br': 'BR',
|
||||
'en': 'EN',
|
||||
'vdd': 'VDD',
|
||||
'gnd': 'GND'}
|
||||
|
||||
|
||||
# You can override the GDS for custom cell using the following:
|
||||
# If it is a list, the first is single port and the second is dual port.
|
||||
# If it is string, it is used for both single and dual port.
|
||||
cell_properties.names["dff"] = "sky130_fd_bd_sram__openram_dff"
|
||||
cell_properties.names["nand2_dec"] = ["sky130_fd_bd_sram__openram_sp_nand2_dec", "sky130_fd_bd_sram__openram_dp_nand2_dec"]
|
||||
cell_properties.names["nand3_dec"] = ["sky130_fd_bd_sram__openram_sp_nand3_dec", "sky130_fd_bd_sram__openram_dp_nand3_dec"]
|
||||
cell_properties.names["nand4_dec"] = ["sky130_fd_bd_sram__openram_sp_nand4_dec", "sky130_fd_bd_sram__openram_dp_nand4_dec"]
|
||||
|
||||
cell_properties.names["bitcell_2port"] = "sky130_fd_bd_sram__openram_dp_cell"
|
||||
cell_properties.names["dummy_bitcell_2port"] = "sky130_fd_bd_sram__openram_dp_cell_dummy"
|
||||
cell_properties.names["replica_bitcell_2port"] = "sky130_fd_bd_sram__openram_dp_cell_replica"
|
||||
cell_properties.names["col_cap_bitcell_2port"] = "sky130_fd_bd_sram__openram_dp_cell_cap_col"
|
||||
cell_properties.names["row_cap_bitcell_2port"] = "sky130_fd_bd_sram__openram_dp_cell_cap_row"
|
||||
cell_properties.names["sense_amp"] = "sky130_fd_bd_sram__openram_sense_amp"
|
||||
cell_properties.names["write_driver"] = "sky130_fd_bd_sram__openram_write_driver"
|
||||
|
||||
array_row_multiple = 2
|
||||
array_col_multiple = 2
|
||||
|
||||
###################################################
|
||||
# Custom layer properties
|
||||
###################################################
|
||||
layer_properties = d.layer_properties()
|
||||
layer_properties.hierarchical_decoder.bus_layer = "m1"
|
||||
layer_properties.hierarchical_decoder.bus_directions = "nonpref"
|
||||
layer_properties.hierarchical_decoder.input_layer = "li"
|
||||
layer_properties.hierarchical_decoder.output_layer = "m2"
|
||||
layer_properties.hierarchical_decoder.vertical_supply = True
|
||||
|
||||
layer_properties.hierarchical_predecode.bus_layer = "m1"
|
||||
layer_properties.hierarchical_predecode.bus_directions = "nonpref"
|
||||
# This is added to allow the column decoder connections on m2
|
||||
layer_properties.hierarchical_predecode.bus_pitch_factor = 1.2
|
||||
layer_properties.hierarchical_predecode.bus_space_factor = 1.5
|
||||
layer_properties.hierarchical_predecode.input_layer = "li"
|
||||
layer_properties.hierarchical_predecode.output_layer = "m2"
|
||||
layer_properties.hierarchical_predecode.vertical_supply = True
|
||||
layer_properties.hierarchical_predecode.force_horizontal_input_contact = True
|
||||
|
||||
layer_properties.bank.stack = "m2_stack"
|
||||
layer_properties.bank.pitch = "m3_pitch"
|
||||
|
||||
layer_properties.column_mux_array.select_layer = "m3"
|
||||
layer_properties.column_mux_array.bitline_layer = "m1"
|
||||
|
||||
layer_properties.port_address.supply_offset = True
|
||||
|
||||
layer_properties.port_data.enable_layer = "m1"
|
||||
layer_properties.port_data.channel_route_bitlines = False
|
||||
|
||||
layer_properties.replica_column.even_rows = True
|
||||
|
||||
layer_properties.wordline_driver.vertical_supply = True
|
||||
|
||||
layer_properties.global_wordline_layer = "m5"
|
||||
|
||||
|
||||
###################################################
|
||||
# Discrete tx bins
|
||||
###################################################
|
||||
# enforce that tx sizes are within 25% of requested size after fingering.
|
||||
accuracy_requirement = 0.75
|
||||
nmos_bins = {
|
||||
0.15 : [0.36, 0.39, 0.42, 0.52, 0.54, 0.55, 0.58, 0.6, 0.61, 0.64, 0.65, 0.74, 0.84, 1.0, 1.26, 1.68, 2.0, 3.0, 5.0, 7.0],
|
||||
0.18 : [0.42, 0.65, 1.0, 3.0, 5.0, 7.0],
|
||||
0.25 : [0.65, 1.0, 3.0, 5.0, 7.0],
|
||||
0.5 : [0.42, 0.55, 0.65, 1.0, 3.0, 5.0, 7.0],
|
||||
1.0 : [0.42, 0.65, 1.0, 3.0, 5.0, 7.0],
|
||||
2.0 : [0.42, 0.65, 1.0, 3.0, 5.0, 7.0],
|
||||
4.0 : [0.42, 0.65, 1.0, 3.0, 5.0, 7.0],
|
||||
8.0 : [0.42, 0.65, 1.0, 3.0, 5.0, 7.0],
|
||||
20.0 : [0.42, 0.65, 1.0, 3.0, 5.0, 7.0]
|
||||
}
|
||||
|
||||
pmos_bins = {
|
||||
0.15 : [0.42, 0.55, 0.64, 0.84, 1.0, 1.12, 1.26, 1.65, 1.68, 2.0, 3.0, 5.0, 7.0],
|
||||
1.0 : [0.42, 0.55, 1.0, 3.0, 5.0, 7.0],
|
||||
2.0 : [0.42, 0.55, 1.0, 3.0, 5.0, 7.0],
|
||||
4.0 : [0.42, 0.55, 1.0, 3.0, 5.0, 7.0],
|
||||
8.0 : [0.42, 0.55, 1.0, 3.0, 5.0, 7.0],
|
||||
0.17 : [0.42, 0.55, 0.64, 0.84, 1.0, 1.12],
|
||||
0.18 : [0.42, 0.55, 0.64, 0.84, 1.0, 1.12, 1.26, 1.68, 2.0, 3.0, 5.0, 7.0],
|
||||
0.25 : [1.0, 3.0, 5.0, 7.0],
|
||||
0.5 : [0.42, 0.55, 1.0, 3.0, 5.0, 7.0],
|
||||
20.0 : [0.42]
|
||||
}
|
||||
###################################################
|
||||
# GDS file info
|
||||
###################################################
|
||||
GDS = {}
|
||||
# gds units
|
||||
# From http://www.cnf.cornell.edu/cnf_spie9.html: "The first
|
||||
# is the size of a database unit in user units. The second is the size
|
||||
# of a database unit in meters. For example, if your library was
|
||||
# created with the default units (user unit = 1 um and 1000 database
|
||||
# units per user unit), then the first number would be 0.001 and the
|
||||
# second number would be 10-9. Typically, the first number is less than
|
||||
# 1, since you use more than 1 database unit per user unit. To
|
||||
# calculate the size of a user unit in meters, divide the second number
|
||||
# by the first."
|
||||
GDS["unit"] = (0.001, 1e-9)
|
||||
#GDS["unit"]=(0.001, 1e-6)
|
||||
|
||||
###################################################
|
||||
# Interconnect stacks
|
||||
###################################################
|
||||
|
||||
poly_stack = ("poly", "contact", "li")
|
||||
active_stack = ("active", "contact", "li")
|
||||
li_stack = ("li", "mcon", "m1")
|
||||
m1_stack = ("m1", "via1", "m2")
|
||||
m2_stack = ("m2", "via2", "m3")
|
||||
m3_stack = ("m3", "via3", "m4")
|
||||
m4_stack = ("m4", "via4", "m5")
|
||||
|
||||
lef_rom_interconnect = ["m1", "m2", "m3", "m4"]
|
||||
|
||||
layer_indices = {"poly": 0,
|
||||
"active": 0,
|
||||
"nwell": 0,
|
||||
"li": 1,
|
||||
"m1": 2,
|
||||
"m2": 3,
|
||||
"m3": 4,
|
||||
"m4": 5,
|
||||
"m5": 6}
|
||||
|
||||
# The FEOL stacks get us up to m1
|
||||
feol_stacks = [poly_stack,
|
||||
active_stack,
|
||||
li_stack]
|
||||
|
||||
# The BEOL stacks are m1 and up
|
||||
beol_stacks = [m1_stack,
|
||||
m2_stack,
|
||||
m3_stack,
|
||||
m4_stack]
|
||||
|
||||
layer_stacks = feol_stacks + beol_stacks
|
||||
|
||||
preferred_directions = {"poly": "V",
|
||||
"active": "V",
|
||||
"li": "V",
|
||||
"m1": "H",
|
||||
"m2": "V",
|
||||
"m3": "H",
|
||||
"m4": "V",
|
||||
"m5": "H"}
|
||||
|
||||
###################################################
|
||||
# GDS Layer Map
|
||||
###################################################
|
||||
|
||||
|
||||
layer = {}
|
||||
layer["active"] = (65, 20) # diff
|
||||
layer["activep"] = (65, 20) # diff
|
||||
layer["tap"] = (65, 44) # tap
|
||||
layer["pwellp"] = (122,16)
|
||||
layer["nwell"] = (64, 20) # nwell
|
||||
layer["dnwell"] = (64,18)
|
||||
layer["nimplant"]= (93, 44) # nsdm
|
||||
layer["pimplant"]= (94, 20) # psdm
|
||||
layer["vtl"] = (125, 44) # lvtn
|
||||
layer["vth"] = (78, 44) # hvtp (pmos only)
|
||||
layer["thkox"] = (8, 0)
|
||||
layer["poly"] = (66, 20)
|
||||
layer["contact"] = (66, 44) # licon1
|
||||
layer["npc"] = (95, 20) # npc (nitride cut)
|
||||
layer["li"] = (67, 20) # active li1
|
||||
layer["mcon"] = (67, 44) # mcon
|
||||
layer["m1"] = (68, 20) # met1
|
||||
layer["m1p"] = (68, 5) # met1 pin
|
||||
layer["via1"] = (68, 44) # via1
|
||||
layer["m2"] = (69, 20) # met2
|
||||
layer["m2p"] = (69, 5) # met2 pin
|
||||
layer["via2"] = (69, 44) # via2
|
||||
layer["m3"] = (70, 20) # met3
|
||||
layer["m3p"] = (70, 5) # met3 pin
|
||||
layer["via3"] = (70, 44) # via3
|
||||
layer["m4"] = (71, 20) # met4
|
||||
layer["m4p"] = (71, 5) # met4 pin
|
||||
layer["via4"] = (71, 44) # via4
|
||||
layer["m5"] = (72, 20) # met5
|
||||
layer["m5p"] = (72, 5) # met5 pin
|
||||
layer["boundary"]= (235, 4)
|
||||
# specific boundary type to define standard cell regions for DRC
|
||||
layer["stdc"] = (81, 4)
|
||||
layer["mem"] = (81, 2)
|
||||
# Not an official sky130 layer, but useful for router debug infos
|
||||
layer["text"]= (234, 5)
|
||||
# Excpected value according to sky130A tech file
|
||||
# If calibre is enabled, these will be swapped below
|
||||
#pin_purpose = 5
|
||||
label_purpose = 5
|
||||
#label_purpose = 16
|
||||
#pin_purpose = 16
|
||||
#label_purpose = 5
|
||||
|
||||
# pin_read purposes
|
||||
special_purposes = {layer["nwell"][0]: [layer["nwell"][1], 5, 59, 16]}
|
||||
#layer_override = {"VNB\x00": ["pwell",122]}
|
||||
layer_override = {"vnb": layer["pwellp"], "VNB": layer["pwellp"]}
|
||||
layer_override_name = {"vnb": "pwellp", "VNB": "pwellp"}
|
||||
layer_override_purpose = {122: (64, 59)}
|
||||
# Layer names for external PDKs
|
||||
layer_names = {}
|
||||
layer_names["active"] = "diff"
|
||||
layer_names["activep"] = "diff"
|
||||
layer_names["tap"] = "tap"
|
||||
layer_names["pwellp"] = "pwellp"
|
||||
layer_names["nwell"] = "nwell"
|
||||
layer_names["dnwell"] = "dnwell"
|
||||
layer_names["nimplant"]= "nsdm"
|
||||
layer_names["pimplant"]= "psdm"
|
||||
layer_names["vtl"] = "lvtn"
|
||||
layer_names["vth"] = "hvtp"
|
||||
layer_names["thkox"] = "thkox"
|
||||
layer_names["poly"] = "poly"
|
||||
layer_names["contact"] = "licon1"
|
||||
layer_names["li"] = "li1"
|
||||
layer_names["mcon"] = "mcon"
|
||||
layer_names["m1"] = "met1"
|
||||
layer_names["m1p"] = "met1"
|
||||
layer_names["via1"] = "via"
|
||||
layer_names["m2"] = "met2"
|
||||
layer_names["m2p"] = "met2"
|
||||
layer_names["via2"] = "via2"
|
||||
layer_names["m3"] = "met3"
|
||||
layer_names["m3p"] = "met3"
|
||||
layer_names["via3"] = "via3"
|
||||
layer_names["m4"] = "met4"
|
||||
layer_names["m4p"] = "met4"
|
||||
layer_names["via4"] = "via4"
|
||||
layer_names["m5p"] = "met5"
|
||||
layer_names["boundary"]= "boundary"
|
||||
layer_names["stdc"] = "areaid.standardc"
|
||||
layer_names["mem"] = "areaid.core"
|
||||
layer_names["text"] = "text"
|
||||
|
||||
|
||||
###################################################
|
||||
# DRC/LVS Rules Setup
|
||||
###################################################
|
||||
|
||||
# technology parameter
|
||||
parameter={}
|
||||
# difftap.2b
|
||||
parameter["min_tx_size"] = 0.150
|
||||
parameter["beta"] = 3
|
||||
|
||||
parameter["6T_inv_nmos_size"] = 0.205
|
||||
parameter["6T_inv_pmos_size"] = 0.09
|
||||
parameter["6T_access_size"] = 0.135
|
||||
|
||||
drc = d.design_rules("sky130")
|
||||
|
||||
# grid size
|
||||
drc["grid"] = 0.005
|
||||
|
||||
#DRC/LVS test set_up
|
||||
# Switching between calibre and magic can be useful for development,
|
||||
# it eventually should be deleted.
|
||||
NDA_PDK_ROOT = os.environ.get("NDA_PDK_ROOT", False)
|
||||
use_calibre = bool(NDA_PDK_ROOT)
|
||||
use_calibre = False
|
||||
use_klayout = False
|
||||
if use_calibre:
|
||||
# Correct order according to s8
|
||||
pin_purpose = 16
|
||||
label_purpose = 5
|
||||
|
||||
drc["drc_rules"] = NDA_PDK_ROOT + "/DRC/Calibre/s8_drcRules"
|
||||
drc["lvs_rules"] = NDA_PDK_ROOT + "/LVS/Calibre/lvs_s8_opts"
|
||||
drc["xrc_rules"] = NDA_PDK_ROOT + "/PEX/xRC/extLvsRules_s8_5lm"
|
||||
drc["layer_map"] = NDA_PDK_ROOT + "/VirtuosoOA/libs/technology_library/s8phirs_10r.layermap"
|
||||
|
||||
# minwidth_tx with contact (no dog bone transistors)
|
||||
# difftap.2b
|
||||
drc["minwidth_tx"] = 0.360
|
||||
drc["minlength_channel"] = 0.150
|
||||
|
||||
drc["pwell_to_nwell"] = 0
|
||||
# nwell.1 Minimum width of nwell/pwell
|
||||
drc.add_layer("nwell",
|
||||
width=0.840,
|
||||
spacing=1.270)
|
||||
|
||||
# poly.1a Minimum width of poly
|
||||
# poly.2 Minimum spacing of poly AND active
|
||||
drc.add_layer("poly",
|
||||
width=0.150,
|
||||
spacing=0.210)
|
||||
# poly.8
|
||||
drc["poly_extend_active"] = 0.13
|
||||
# Not a rule
|
||||
drc["poly_to_contact"] = 0
|
||||
# poly.7 Minimum enclosure of active around gate
|
||||
drc["active_enclose_gate"] = 0.075
|
||||
# poly.4 Minimum spacing of field poly to active
|
||||
drc["poly_to_active"] = 0.075
|
||||
# poly.2 Minimum spacing of field poly
|
||||
drc["poly_to_field_poly"] = 0.210
|
||||
|
||||
# difftap.1 Minimum width of active
|
||||
# difftap.3 Minimum spacing of active
|
||||
drc.add_layer("active",
|
||||
width=0.150,
|
||||
spacing=0.270)
|
||||
# difftap.8
|
||||
drc.add_enclosure("nwell",
|
||||
layer="active",
|
||||
enclosure=0.18,
|
||||
extension=0.18)
|
||||
|
||||
# nsd/psd.5a
|
||||
drc.add_enclosure("implant",
|
||||
layer="active",
|
||||
enclosure=0.125)
|
||||
|
||||
# Same as active enclosure?
|
||||
drc["implant_to_contact"] = 0.070
|
||||
# nsd/psd.1 nsd/psd.2
|
||||
drc.add_layer("implant",
|
||||
width=0.380,
|
||||
spacing=0.380,
|
||||
area=0.265)
|
||||
|
||||
# licon.1, licon.2
|
||||
drc.add_layer("contact",
|
||||
width=0.170,
|
||||
spacing=0.170)
|
||||
# licon.5c (0.06 extension), (licon.7 for extension)
|
||||
drc.add_enclosure("active",
|
||||
layer="contact",
|
||||
enclosure=0.040,
|
||||
extension=0.060)
|
||||
# licon.7
|
||||
drc["tap_extend_contact"] = 0.120
|
||||
|
||||
# licon.8 Minimum enclosure of poly around contact
|
||||
drc.add_enclosure("poly",
|
||||
layer="contact",
|
||||
enclosure=0.08,
|
||||
extension=0.08)
|
||||
# licon.11a
|
||||
drc["active_contact_to_gate"] = 0.050
|
||||
# npc.4 > licon.14 0.19 > licon.11a
|
||||
drc["poly_contact_to_gate"] = 0.270
|
||||
# licon.15
|
||||
drc["npc_enclose_poly"] = 0.1
|
||||
|
||||
# li.1, li.3
|
||||
drc.add_layer("li",
|
||||
width=0.170,
|
||||
spacing=0.170)
|
||||
|
||||
# licon.5
|
||||
drc.add_enclosure("li",
|
||||
layer="contact",
|
||||
enclosure=0,
|
||||
extension=0.080)
|
||||
|
||||
drc.add_enclosure("li",
|
||||
layer="mcon",
|
||||
enclosure=0,
|
||||
extension=0.080)
|
||||
# mcon.1, mcon.2
|
||||
drc.add_layer("mcon",
|
||||
width=0.170,
|
||||
spacing=0.210)
|
||||
|
||||
# m1.1 Minimum width of metal1
|
||||
# m1.2 Minimum spacing of metal1
|
||||
# m1.6 Minimum area of metal1
|
||||
drc.add_layer("m1",
|
||||
width=0.140,
|
||||
spacing=0.140,
|
||||
area=0.083)
|
||||
# m1.4 Minimum enclosure of metal1
|
||||
# m1.5 Minimum enclosure around contact on two opposite sides
|
||||
drc.add_enclosure("m1",
|
||||
layer="mcon",
|
||||
enclosure=0.030,
|
||||
extension=0.060)
|
||||
# via.4a Minimum enclosure around via1
|
||||
# via.5a Minimum enclosure around via1 on two opposite sides
|
||||
drc.add_enclosure("m1",
|
||||
layer="via1",
|
||||
enclosure=0.055,
|
||||
extension=0.085)
|
||||
|
||||
# via.1a Minimum width of via1
|
||||
# via.2 Minimum spacing of via1
|
||||
drc.add_layer("via1",
|
||||
width=0.150,
|
||||
spacing=0.170)
|
||||
|
||||
# m2.1 Minimum width of intermediate metal
|
||||
# m2.2 Minimum spacing of intermediate metal
|
||||
# m2.6 Minimum area of metal2
|
||||
drc.add_layer("m2",
|
||||
width=0.140,
|
||||
spacing=0.140,
|
||||
area=0.0676)
|
||||
# m2.4 Minimum enclosure around via1
|
||||
# m2.5 Minimum enclosure around via1 on two opposite sides
|
||||
drc.add_enclosure("m2",
|
||||
layer="via1",
|
||||
enclosure=0.055,
|
||||
extension=0.085)
|
||||
# via2.4 Minimum enclosure around via2
|
||||
# via2.5 Minimum enclosure around via2 on two opposite sides
|
||||
drc.add_enclosure("m2",
|
||||
layer="via2",
|
||||
enclosure=0.040,
|
||||
extension=0.085)
|
||||
|
||||
# via2.1a Minimum width of Via2
|
||||
# via2.2 Minimum spacing of Via2
|
||||
drc.add_layer("via2",
|
||||
width=0.200,
|
||||
spacing=0.200)
|
||||
|
||||
# m3.1 Minimum width of metal3
|
||||
# m3.2 Minimum spacing of metal3
|
||||
# m3.6 Minimum area of metal3
|
||||
drc.add_layer("m3",
|
||||
width=0.300,
|
||||
spacing=0.300,
|
||||
area=0.240)
|
||||
# m3.4 Minimum enclosure around via2
|
||||
drc.add_enclosure("m3",
|
||||
layer="via2",
|
||||
enclosure=0.065)
|
||||
# via3.4 Minimum enclosure around via3
|
||||
# via3.5 Minimum enclosure around via3 on two opposite sides
|
||||
drc.add_enclosure("m3",
|
||||
layer="via3",
|
||||
enclosure=0.060,
|
||||
extension=0.090)
|
||||
|
||||
# via3.1 Minimum width of Via3
|
||||
# via3.2 Minimum spacing of Via3
|
||||
drc.add_layer("via3",
|
||||
width=0.200,
|
||||
spacing=0.200)
|
||||
|
||||
# m4.1 Minimum width of metal4
|
||||
# m4.2 Minimum spacing of metal4
|
||||
# m4.7 Minimum area of metal4
|
||||
drc.add_layer("m4",
|
||||
width=0.300,
|
||||
spacing=0.300,
|
||||
area=0.240)
|
||||
# m4.3 Minimum enclosure around via3
|
||||
drc.add_enclosure("m4",
|
||||
layer="via3",
|
||||
enclosure=0.065)
|
||||
# FIXME: Wrong rule m4.3 Minimum enclosure around via3
|
||||
drc.add_enclosure("m4",
|
||||
layer="via4",
|
||||
enclosure=0.060)
|
||||
|
||||
|
||||
# via4.1 Minimum width of Via4
|
||||
# via4.2 Minimum spacing of Via4
|
||||
drc.add_layer("via4",
|
||||
width=0.800,
|
||||
spacing=0.800)
|
||||
|
||||
# FIXME: Wrong rules
|
||||
# m5.1 Minimum width of metal5
|
||||
# m5.2 Minimum spacing of metal5
|
||||
# m5.7 Minimum area of metal5
|
||||
drc.add_layer("m5",
|
||||
width=1.600,
|
||||
spacing=1.600,
|
||||
area=4.000)
|
||||
# m5.3 Minimum enclosure around via4
|
||||
drc.add_enclosure("m5",
|
||||
layer="via4",
|
||||
enclosure=0.310)
|
||||
|
||||
|
||||
|
||||
# Metal 5-10 are ommitted
|
||||
|
||||
###################################################
|
||||
# Spice Simulation Parameters
|
||||
###################################################
|
||||
|
||||
# spice info
|
||||
spice = {}
|
||||
spice["nmos"] = "sky130_fd_pr__nfet_01v8"
|
||||
spice["pmos"] = "sky130_fd_pr__pfet_01v8"
|
||||
spice["power"]="vccd1"
|
||||
spice["ground"]="vssd1"
|
||||
|
||||
# whether or not the device model is actually a subckt
|
||||
spice["device_prefix"] = "X"
|
||||
|
||||
spice["fet_libraries"] = { "TT": [[os.environ.get("SPICE_MODEL_DIR") + "/sky130.lib.spice", "tt"]],
|
||||
"SS": [[os.environ.get("SPICE_MODEL_DIR") + "/sky130.lib.spice", "ss"]],
|
||||
"FF": [[os.environ.get("SPICE_MODEL_DIR") + "/sky130.lib.spice", "ff"]],
|
||||
"SF": [[os.environ.get("SPICE_MODEL_DIR") + "/sky130.lib.spice", "sf"]],
|
||||
"FS": [[os.environ.get("SPICE_MODEL_DIR") + "/sky130.lib.spice", "fs"]] }
|
||||
|
||||
# spice stimulus related variables
|
||||
spice["feasible_period"] = 10 # estimated feasible period in ns
|
||||
spice["supply_voltages"] = [1.7, 1.8, 1.9] # Supply voltage corners in [Volts]
|
||||
spice["nom_supply_voltage"] = 1.8 # Nominal supply voltage in [Volts]
|
||||
spice["rise_time"] = 0.005 # rise time in [Nano-seconds]
|
||||
spice["fall_time"] = 0.005 # fall time in [Nano-seconds]
|
||||
spice["temperatures"] = [0, 25, 100] # Temperature corners (celcius)
|
||||
spice["nom_temperature"] = 25 # Nominal temperature (celcius)
|
||||
|
||||
# analytical delay parameters
|
||||
spice["nom_threshold"] = 0.49 # Typical Threshold voltage in Volts
|
||||
spice["wire_unit_r"] = 0.125 # Unit wire resistance in ohms/square
|
||||
spice["wire_unit_c"] = 0.134 # Unit wire capacitance ff/um^2
|
||||
spice["min_tx_drain_c"] = 0.7 # Minimum transistor drain capacitance in ff
|
||||
spice["min_tx_gate_c"] = 0.2 # Minimum transistor gate capacitance in ff
|
||||
spice["dff_setup"] = 102.5391 # DFF setup time in ps
|
||||
spice["dff_hold"] = -56 # DFF hold time in ps
|
||||
spice["dff_in_cap"] = 6.89 # Input capacitance (D) [Femto-farad]
|
||||
spice["dff_out_cap"] = 6.89 # Output capacitance (Q) [Femto-farad]
|
||||
|
||||
# analytical power parameters, many values are temporary
|
||||
spice["bitcell_leakage"] = 1 # Leakage power of a single bitcell in nW
|
||||
spice["inv_leakage"] = 1 # Leakage power of inverter in nW
|
||||
spice["nand2_leakage"] = 1 # Leakage power of 2-input nand in nW
|
||||
spice["nand3_leakage"] = 1 # Leakage power of 3-input nand in nW
|
||||
spice["nand4_leakage"] = 1 # Leakage power of 4-input nand in nW
|
||||
spice["nor2_leakage"] = 1 # Leakage power of 2-input nor in nW
|
||||
spice["dff_leakage"] = 1 # Leakage power of flop in nW
|
||||
|
||||
spice["default_event_frequency"] = 100 # Default event activity of every gate. MHz
|
||||
|
||||
# Parameters related to sense amp enable timing and delay chain/RBL sizing
|
||||
parameter["le_tau"] = 2.25 # In pico-seconds.
|
||||
parameter["cap_relative_per_ff"] = 7.5 # Units of Relative Capacitance/ Femto-Farad
|
||||
parameter["dff_clk_cin"] = 30.6 # relative capacitance
|
||||
parameter["6tcell_wl_cin"] = 3 # relative capacitance
|
||||
parameter["min_inv_para_delay"] = 2.4 # Tau delay units
|
||||
parameter["sa_en_pmos_size"] = 0.72 # micro-meters
|
||||
parameter["sa_en_nmos_size"] = 0.27 # micro-meters
|
||||
parameter["sa_inv_pmos_size"] = 0.54 # micro-meters
|
||||
parameter["sa_inv_nmos_size"] = 0.27 # micro-meters
|
||||
parameter["bitcell_drain_cap"] = 0.1 # In Femto-Farad, approximation of drain capacitance
|
||||
|
||||
###################################################
|
||||
# Technology Tool Preferences
|
||||
###################################################
|
||||
|
||||
if use_calibre:
|
||||
drc_name = "calibre"
|
||||
lvs_name = "calibre"
|
||||
pex_name = "calibre"
|
||||
elif use_klayout:
|
||||
drc_name = "klayout"
|
||||
lvs_name = "klayout"
|
||||
pex_name = "klayout"
|
||||
else:
|
||||
drc_name = "magic"
|
||||
lvs_name = "netgen"
|
||||
pex_name = "magic"
|
||||
|
||||
|
||||
# This is used by uniqify to not rename the library cells
|
||||
library_prefix_name = "sky130_fd_bd_sram__"
|
||||
# List of cells to skip running DRC/LVS on directly
|
||||
# This will look for a maglef file and copy it over the mag file
|
||||
# before DRC after extraction
|
||||
|
||||
# gds flatglob sky130_fd_bd_sram__openram_sp_cell_opt1a_cell
|
||||
# gds flatglob sky130_fd_bd_sram__openram_sp_cell_opt1a_replica_ce
|
||||
# gds flatglob sky130_fd_bd_sram__openram_sp_cell_opt1_replica_cell
|
||||
# gds flatglob sky130_fd_bd_sram__openram_sp_cell_opt1_replica_ce
|
||||
# gds flatglob sky130_fd_bd_sram__openram_sp_cell_opt1_replica_cell
|
||||
# gds flatglob sky130_fd_bd_sram__openram_sp_cell_opt1a_cell
|
||||
# gds flatglob sky130_fd_bd_sram__sram_sp_cell_fom_serifs
|
||||
|
||||
flatglob = ["*_?mos_m*",
|
||||
"sky130_fd_bd_sram__sram_sp_cell_fom_serifs",
|
||||
|
||||
"sky130_fd_bd_sram__sram_sp_cell",
|
||||
"sky130_fd_bd_sram__openram_sp_cell_opt1_replica_cell",
|
||||
"sky130_fd_bd_sram__openram_sp_cell_opt1a_replica_cell",
|
||||
|
||||
"sky130_fd_bd_sram__sram_sp_cell_opt1_ce",
|
||||
"sky130_fd_bd_sram__openram_sp_cell_opt1_replica_ce",
|
||||
"sky130_fd_bd_sram__openram_sp_cell_opt1a_replica_ce",
|
||||
"sky130_fd_bd_sram__sram_sp_wlstrap_ce",
|
||||
"sky130_fd_bd_sram__sram_sp_wlstrap_p_ce"]
|
||||
|
||||
blackbox_cells = ["sky130_fd_bd_sram__openram_dp_cell",
|
||||
"sky130_fd_bd_sram__openram_dp_cell_dummy",
|
||||
"sky130_fd_bd_sram__openram_dp_cell_replica",
|
||||
|
||||
"sky130_fd_bd_sram__sram_sp_cell_opt1a",
|
||||
"sky130_fd_bd_sram__openram_sp_cell_opt1a_dummy",
|
||||
"sky130_fd_bd_sram__sram_sp_cell_opt1_ce",
|
||||
"sky130_fd_bd_sram__sram_sp_cell_opt1",
|
||||
"sky130_fd_bd_sram__openram_sp_cell_opt1_replica",
|
||||
"sky130_fd_bd_sram__openram_sp_cell_opt1a_replica",
|
||||
"sky130_fd_bd_sram__sram_sp_colend",
|
||||
"sky130_fd_bd_sram__sram_sp_colend_cent",
|
||||
"sky130_fd_bd_sram__sram_sp_colend_p_cent",
|
||||
"sky130_fd_bd_sram__sram_sp_colenda",
|
||||
"sky130_fd_bd_sram__sram_sp_colenda_cent",
|
||||
"sky130_fd_bd_sram__sram_sp_colenda_p_cent",
|
||||
"sky130_fd_bd_sram__sram_sp_rowend",
|
||||
"sky130_fd_bd_sram__sram_sp_rowenda",
|
||||
"sky130_fd_bd_sram__openram_sp_rowend_replica",
|
||||
"sky130_fd_bd_sram__openram_sp_rowenda_replica",
|
||||
"sky130_fd_bd_sram__sram_sp_corner",
|
||||
"sky130_fd_bd_sram__sram_sp_cornera",
|
||||
"sky130_fd_bd_sram__sram_sp_cornerb",
|
||||
"sky130_fd_bd_sram__sram_sp_wlstrapa",
|
||||
"sky130_fd_bd_sram__sram_sp_wlstrap_ce",
|
||||
"sky130_fd_bd_sram__sram_sp_wlstrap",
|
||||
"sky130_fd_bd_sram__sram_sp_wlstrap_p_ce",
|
||||
"sky130_fd_bd_sram__sram_sp_wlstrap_p"]
|
||||
if not hasattr(OPTS, 'tech_file'):
|
||||
OPTS.tech_file = 'tech_cypress_cell'
|
||||
#TODO: FIX THIS TERRIBLE HACK JUST FOR TESTING
|
||||
exec('from {} import *'.format(OPTS.tech_file))
|
||||
|
||||
@@ -0,0 +1,857 @@
|
||||
#!/usr/bin/env python3
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2023 Regents of the University of California
|
||||
# All rights reserved.
|
||||
#
|
||||
|
||||
|
||||
import os
|
||||
from openram import drc as d
|
||||
|
||||
"""
|
||||
File containing the process technology parameters for Skywater 130nm.
|
||||
"""
|
||||
|
||||
###################################################
|
||||
# Custom modules
|
||||
###################################################
|
||||
|
||||
# This uses the default classes to instantiate module from
|
||||
# '$OPENRAM_HOME/compiler/modules'.
|
||||
# Using tech_modules['cellname'] you can override each class by providing a custom
|
||||
# implementation in '$OPENRAM_TECHDIR/modules/'
|
||||
# For example: tech_modules["contact"] = "contact_freepdk45"
|
||||
tech_modules = d.module_type()
|
||||
|
||||
|
||||
# These modules have been hand designed and provided in this repository.
|
||||
tech_modules["nand2_dec"] = "nand2_dec"
|
||||
tech_modules["nand3_dec"] = "nand3_dec"
|
||||
tech_modules["nand4_dec"] = "nand4_dec"
|
||||
|
||||
# Override default OpenRAM modules to sky130 modules
|
||||
# These are for single port and dual port as a list,
|
||||
# or for both if there is no list,
|
||||
# or only applicable to one if there is no list.
|
||||
|
||||
#tech_modules["bitcell_1port"] = "sky130_bitcell"
|
||||
#tech_modules["replica_bitcell_1port"] = "sky130_replica_bitcell"
|
||||
#tech_modules["dummy_bitcell_1port"] = "sky130_dummy_bitcell"
|
||||
|
||||
tech_modules["replica_bitcell_2port"] = "replica_bitcell_2port"
|
||||
tech_modules["dummy_bitcell_2port"] = "dummy_bitcell_2port"
|
||||
tech_modules["bitcell_2port"] = "bitcell_2port"
|
||||
|
||||
tech_modules["bitcell_array"] = ["bitcell_array", "bitcell_array"]
|
||||
tech_modules["replica_bitcell_array"] = ["replica_bitcell_array", "replica_bitcell_array"]
|
||||
tech_modules["capped_replica_bitcell_array"] = ["capped_replica_bitcell_array", "capped_replica_bitcell_array"]
|
||||
tech_modules["dummy_array"] = ["dummy_array", "dummy_array"]
|
||||
|
||||
tech_modules["replica_column"] = ["replica_column", "replica_column"]
|
||||
|
||||
tech_modules["col_cap_array"] = ["col_cap_array", "col_cap_array"]
|
||||
tech_modules["col_cap"] = ["col_cap_bitcell_1port", "col_cap_bitcell_2port"]
|
||||
tech_modules["corner"] = ["sky130_corner", None]
|
||||
tech_modules["internal"] = ["sky130_internal", None]
|
||||
tech_modules["row_cap_array"] = ["sky130_row_cap_array", "row_cap_array"]
|
||||
tech_modules["row_cap"] = ["sky130_row_cap", "row_cap_bitcell_2port"]
|
||||
|
||||
# These modules are auto-generated from the nand decoders above and are not
|
||||
# found in this.
|
||||
tech_modules["buf_dec"] = "pbuf_dec"
|
||||
tech_modules["inv_dec"] = "pinv_dec"
|
||||
tech_modules["and2_dec"] = "and2_dec"
|
||||
tech_modules["and3_dec"] = "and3_dec"
|
||||
tech_modules["and4_dec"] = "and4_dec"
|
||||
|
||||
###################################################
|
||||
# Custom cell properties
|
||||
###################################################
|
||||
cell_properties = d.cell_properties()
|
||||
|
||||
cell_properties.power_name = 'VPWR'
|
||||
cell_properties.ground_name = 'VGND'
|
||||
|
||||
cell_properties.bitcell_power_pin_directions = ("V", "V")
|
||||
|
||||
cell_properties.bitcell_1port.mirror.x = True
|
||||
cell_properties.bitcell_1port.mirror.y = True
|
||||
cell_properties.bitcell_1port.end_caps = False
|
||||
cell_properties.bitcell_1port.has_corners = True
|
||||
|
||||
cell_properties.bitcell_1port.boundary_layer = "boundary"
|
||||
cell_properties.bitcell_1port.port_order = ['bl', 'br', 'wl', 'vdd', 'gnd']
|
||||
cell_properties.bitcell_1port.port_types = ["INPUT", "INPUT", "GROUND", "POWER", "OUTPUT"]
|
||||
cell_properties.bitcell_1port.port_map = {'bl': 'BL',
|
||||
'br': 'BR',
|
||||
'gnd': 'VGND',
|
||||
'vdd': 'VPWR',
|
||||
'wl': 'WL'}
|
||||
|
||||
|
||||
|
||||
|
||||
cell_properties.bitcell_1port.wl_layer = "m2"
|
||||
cell_properties.bitcell_1port.bl_layer = "m1"
|
||||
cell_properties.bitcell_1port.vdd_layer = "m1"
|
||||
cell_properties.bitcell_1port.vdd_dir = "V"
|
||||
cell_properties.bitcell_1port.gnd_layer = "m1"
|
||||
cell_properties.bitcell_1port.gnd_dir = "V"
|
||||
|
||||
cell_properties.bitcell_2port.mirror.x = True
|
||||
cell_properties.bitcell_2port.mirror.y = True
|
||||
cell_properties.bitcell_2port.end_caps = True
|
||||
cell_properties.bitcell_2port.has_corners = True
|
||||
cell_properties.bitcell_2port.port_order = ['bl0', 'br0', 'bl1', 'br1', 'wl0', 'wl1', 'vdd', 'gnd']
|
||||
cell_properties.bitcell_2port.port_map = {'bl0': 'BL0',
|
||||
'br0': 'BR0',
|
||||
'bl1': 'BL1',
|
||||
'br1': 'BR1',
|
||||
'wl0': 'WL0',
|
||||
'wl1': 'WL1',
|
||||
'vdd': 'VDD',
|
||||
'gnd': 'GND'}
|
||||
|
||||
cell_properties.bitcell_1port.wl_layer = "m2"
|
||||
cell_properties.bitcell_1port.vdd_layer = "m1"
|
||||
cell_properties.bitcell_1port.vdd_dir = "V"
|
||||
cell_properties.bitcell_1port.gnd_layer = "m1"
|
||||
cell_properties.bitcell_1port.gnd_dir = "V"
|
||||
cell_properties.bitcell_2port.wl_layer = "m2"
|
||||
cell_properties.bitcell_2port.vdd_layer = "m1"
|
||||
cell_properties.bitcell_2port.vdd_dir = "H"
|
||||
cell_properties.bitcell_2port.gnd_layer = "m2"
|
||||
cell_properties.bitcell_2port.gnd_dir = "H"
|
||||
|
||||
cell_properties.col_cap_1port_bitcell = d.cell(['bl', 'br', 'vdd', 'gnd',],
|
||||
['INPUT', 'INPUT','POWER', 'GROUND', ],
|
||||
{'bl': 'bl',
|
||||
'br': 'br',
|
||||
'vdd': 'vdd',
|
||||
'gnd': 'gnd',})
|
||||
cell_properties.col_cap_1port_bitcell.boundary_layer = "boundary"
|
||||
|
||||
cell_properties.col_cap_1port_strap_power = d.cell(['vdd', 'vpb', 'vnb'],
|
||||
['POWER', 'BIAS', 'BIAS'],
|
||||
{'vnb': 'VNB',
|
||||
'vpb': 'VPB',
|
||||
'vdd': 'VPWR'})
|
||||
cell_properties.col_cap_1port_strap_power.boundary_layer = "boundary"
|
||||
|
||||
cell_properties.col_cap_1port_strap_ground = d.cell(['gnd', 'vpb', 'vnb'],
|
||||
['GROUND', 'BIAS', 'BIAS'],
|
||||
{'vnb': 'VNB',
|
||||
'vpb': 'VPB',
|
||||
'gnd': 'VGND'})
|
||||
cell_properties.col_cap_1port_strap_ground.boundary_layer = "boundary"
|
||||
|
||||
cell_properties.row_cap_1port_cell = d.cell(['vdd', 'wl'],
|
||||
['POWER', 'INPUT'],
|
||||
{'wl': 'WL',
|
||||
'vdd': 'VPWR'})
|
||||
cell_properties.row_cap_1port_cell.boundary_layer = "boundary"
|
||||
|
||||
cell_properties.col_cap_2port.port_order = ['bl0', 'br0', 'bl1', 'br1', 'vdd']
|
||||
cell_properties.col_cap_2port.port_map = {'bl0': 'BL0',
|
||||
'br0': 'BR0',
|
||||
'bl1': 'BL1',
|
||||
'br1': 'BR1',
|
||||
'vdd': 'VDD'}
|
||||
|
||||
cell_properties.row_cap_2port.port_order = ['wl0', 'wl1', 'gnd']
|
||||
cell_properties.row_cap_2port.port_map = {'wl0': 'WL0',
|
||||
'wl1': 'WL1',
|
||||
'gnd': 'GND'}
|
||||
|
||||
|
||||
cell_properties.ptx.bin_spice_models = True
|
||||
cell_properties.ptx.model_is_subckt = True
|
||||
|
||||
cell_properties.pgate.add_implants = True
|
||||
|
||||
cell_properties.use_strap = False
|
||||
cell_properties.strap_module = "internal"
|
||||
cell_properties.strap_version = "wlstrap"
|
||||
|
||||
cell_properties.dff.port_order = ['D', 'Q', 'clk', 'vdd', 'gnd']
|
||||
cell_properties.dff.port_map = {'D': 'D',
|
||||
'Q': 'Q',
|
||||
'clk': 'CLK',
|
||||
'vdd': 'VDD',
|
||||
'gnd': 'GND'}
|
||||
|
||||
cell_properties.nand2_dec.port_order = ['A', 'B', 'Z', 'vdd', 'gnd']
|
||||
cell_properties.nand2_dec.port_map = {'A': 'A',
|
||||
'B': 'B',
|
||||
'Z': 'Z',
|
||||
'vdd': 'VDD',
|
||||
'gnd': 'GND'}
|
||||
|
||||
cell_properties.nand3_dec.port_order = ['A', 'B', 'C', 'Z', 'vdd', 'gnd']
|
||||
cell_properties.nand3_dec.port_map = {'A': 'A',
|
||||
'B': 'B',
|
||||
'C': 'C',
|
||||
'Z': 'Z',
|
||||
'vdd': 'VDD',
|
||||
'gnd': 'GND'}
|
||||
|
||||
cell_properties.nand4_dec.port_order = ['A', 'B', 'C', 'D', 'Z', 'vdd', 'gnd']
|
||||
cell_properties.nand4_dec.port_map = {'A': 'A',
|
||||
'B': 'B',
|
||||
'C': 'C',
|
||||
'D': 'D',
|
||||
'Z': 'Z',
|
||||
'vdd': 'VDD',
|
||||
'gnd': 'GND'}
|
||||
|
||||
cell_properties.sense_amp.port_order = ['bl', 'br', 'dout', 'en', 'vdd', 'gnd']
|
||||
cell_properties.sense_amp.port_map = {'bl': 'BL',
|
||||
'br': 'BR',
|
||||
'dout': 'DOUT',
|
||||
'en': 'EN',
|
||||
'vdd': 'VDD',
|
||||
'gnd': 'GND'}
|
||||
|
||||
cell_properties.write_driver.port_order = ['din', 'bl', 'br', 'en', 'vdd', 'gnd']
|
||||
cell_properties.write_driver.port_map = {'din': 'DIN',
|
||||
'bl': 'BL',
|
||||
'br': 'BR',
|
||||
'en': 'EN',
|
||||
'vdd': 'VDD',
|
||||
'gnd': 'GND'}
|
||||
|
||||
|
||||
# You can override the GDS for custom cell using the following:
|
||||
# If it is a list, the first is single port and the second is dual port.
|
||||
# If it is string, it is used for both single and dual port.
|
||||
cell_properties.names["dff"] = "sky130_fd_bd_sram__openram_dff"
|
||||
cell_properties.names["nand2_dec"] = ["sky130_fd_bd_sram__openram_dp_nand2_dec", "sky130_fd_bd_sram__openram_dp_nand2_dec"]
|
||||
cell_properties.names["nand3_dec"] = ["sky130_fd_bd_sram__openram_dp_nand3_dec", "sky130_fd_bd_sram__openram_dp_nand3_dec"]
|
||||
cell_properties.names["nand4_dec"] = ["sky130_fd_bd_sram__openram_dp_nand4_dec", "sky130_fd_bd_sram__openram_dp_nand4_dec"]
|
||||
|
||||
cell_properties.names["bitcell_1port"] = "sky130_custom_cell"
|
||||
cell_properties.names["replica_bitcell_1port"] = "sky130_custom_replica"
|
||||
cell_properties.names["dummy_bitcell_1port"] = "sky130_custom_dummy"
|
||||
|
||||
cell_properties.names["bitcell_2port"] = "sky130_fd_bd_sram__openram_dp_cell"
|
||||
cell_properties.names["dummy_bitcell_2port"] = "sky130_fd_bd_sram__openram_dp_cell_dummy"
|
||||
cell_properties.names["replica_bitcell_2port"] = "sky130_fd_bd_sram__openram_dp_cell_replica"
|
||||
cell_properties.names["col_cap_bitcell_2port"] = "sky130_fd_bd_sram__openram_dp_cell_cap_col"
|
||||
cell_properties.names["row_cap_bitcell_2port"] = "sky130_fd_bd_sram__openram_dp_cell_cap_row"
|
||||
cell_properties.names["sense_amp"] = "sky130_fd_bd_sram__openram_sense_amp"
|
||||
cell_properties.names["write_driver"] = "sky130_fd_bd_sram__openram_write_driver"
|
||||
|
||||
array_row_multiple = 2
|
||||
array_col_multiple = 2
|
||||
|
||||
###################################################
|
||||
# Custom layer properties
|
||||
###################################################
|
||||
layer_properties = d.layer_properties()
|
||||
layer_properties.hierarchical_decoder.bus_layer = "m1"
|
||||
layer_properties.hierarchical_decoder.bus_directions = "nonpref"
|
||||
layer_properties.hierarchical_decoder.input_layer = "li"
|
||||
layer_properties.hierarchical_decoder.output_layer = "m2"
|
||||
layer_properties.hierarchical_decoder.vertical_supply = True
|
||||
|
||||
layer_properties.hierarchical_predecode.bus_layer = "m1"
|
||||
layer_properties.hierarchical_predecode.bus_directions = "nonpref"
|
||||
# This is added to allow the column decoder connections on m2
|
||||
layer_properties.hierarchical_predecode.bus_pitch_factor = 1.2
|
||||
layer_properties.hierarchical_predecode.bus_space_factor = 1.5
|
||||
layer_properties.hierarchical_predecode.input_layer = "li"
|
||||
layer_properties.hierarchical_predecode.output_layer = "m2"
|
||||
layer_properties.hierarchical_predecode.vertical_supply = True
|
||||
layer_properties.hierarchical_predecode.force_horizontal_input_contact = True
|
||||
|
||||
layer_properties.bank.stack = "m2_stack"
|
||||
layer_properties.bank.pitch = "m3_pitch"
|
||||
|
||||
layer_properties.column_mux_array.select_layer = "m3"
|
||||
layer_properties.column_mux_array.bitline_layer = "m1"
|
||||
|
||||
layer_properties.port_address.supply_offset = True
|
||||
|
||||
layer_properties.port_data.enable_layer = "m1"
|
||||
layer_properties.port_data.channel_route_bitlines = False
|
||||
|
||||
layer_properties.replica_column.even_rows = False
|
||||
|
||||
layer_properties.wordline_driver.vertical_supply = True
|
||||
|
||||
layer_properties.global_wordline_layer = "m5"
|
||||
|
||||
|
||||
###################################################
|
||||
# Discrete tx bins
|
||||
###################################################
|
||||
# enforce that tx sizes are within 25% of requested size after fingering.
|
||||
accuracy_requirement = 0.75
|
||||
nmos_bins = {
|
||||
0.15 : [0.36, 0.39, 0.42, 0.52, 0.54, 0.55, 0.58, 0.6, 0.61, 0.64, 0.65, 0.74, 0.84, 1.0, 1.26, 1.68, 2.0, 3.0, 5.0, 7.0],
|
||||
0.18 : [0.42, 0.65, 1.0, 3.0, 5.0, 7.0],
|
||||
0.25 : [0.65, 1.0, 3.0, 5.0, 7.0],
|
||||
0.5 : [0.42, 0.55, 0.65, 1.0, 3.0, 5.0, 7.0],
|
||||
1.0 : [0.42, 0.65, 1.0, 3.0, 5.0, 7.0],
|
||||
2.0 : [0.42, 0.65, 1.0, 3.0, 5.0, 7.0],
|
||||
4.0 : [0.42, 0.65, 1.0, 3.0, 5.0, 7.0],
|
||||
8.0 : [0.42, 0.65, 1.0, 3.0, 5.0, 7.0],
|
||||
20.0 : [0.42, 0.65, 1.0, 3.0, 5.0, 7.0]
|
||||
}
|
||||
|
||||
pmos_bins = {
|
||||
0.15 : [0.42, 0.55, 0.64, 0.84, 1.0, 1.12, 1.26, 1.65, 1.68, 2.0, 3.0, 5.0, 7.0],
|
||||
1.0 : [0.42, 0.55, 1.0, 3.0, 5.0, 7.0],
|
||||
2.0 : [0.42, 0.55, 1.0, 3.0, 5.0, 7.0],
|
||||
4.0 : [0.42, 0.55, 1.0, 3.0, 5.0, 7.0],
|
||||
8.0 : [0.42, 0.55, 1.0, 3.0, 5.0, 7.0],
|
||||
0.17 : [0.42, 0.55, 0.64, 0.84, 1.0, 1.12],
|
||||
0.18 : [0.42, 0.55, 0.64, 0.84, 1.0, 1.12, 1.26, 1.68, 2.0, 3.0, 5.0, 7.0],
|
||||
0.25 : [1.0, 3.0, 5.0, 7.0],
|
||||
0.5 : [0.42, 0.55, 1.0, 3.0, 5.0, 7.0],
|
||||
20.0 : [0.42]
|
||||
}
|
||||
###################################################
|
||||
# GDS file info
|
||||
###################################################
|
||||
GDS = {}
|
||||
# gds units
|
||||
# From http://www.cnf.cornell.edu/cnf_spie9.html: "The first
|
||||
# is the size of a database unit in user units. The second is the size
|
||||
# of a database unit in meters. For example, if your library was
|
||||
# created with the default units (user unit = 1 um and 1000 database
|
||||
# units per user unit), then the first number would be 0.001 and the
|
||||
# second number would be 10-9. Typically, the first number is less than
|
||||
# 1, since you use more than 1 database unit per user unit. To
|
||||
# calculate the size of a user unit in meters, divide the second number
|
||||
# by the first."
|
||||
GDS["unit"] = (0.001, 1e-9)
|
||||
#GDS["unit"]=(0.001, 1e-6)
|
||||
|
||||
###################################################
|
||||
# Interconnect stacks
|
||||
###################################################
|
||||
|
||||
poly_stack = ("poly", "contact", "li")
|
||||
active_stack = ("active", "contact", "li")
|
||||
li_stack = ("li", "mcon", "m1")
|
||||
m1_stack = ("m1", "via1", "m2")
|
||||
m2_stack = ("m2", "via2", "m3")
|
||||
m3_stack = ("m3", "via3", "m4")
|
||||
m4_stack = ("m4", "via4", "m5")
|
||||
|
||||
lef_rom_interconnect = ["m1", "m2", "m3", "m4"]
|
||||
|
||||
layer_indices = {"poly": 0,
|
||||
"active": 0,
|
||||
"nwell": 0,
|
||||
"li": 1,
|
||||
"m1": 2,
|
||||
"m2": 3,
|
||||
"m3": 4,
|
||||
"m4": 5,
|
||||
"m5": 6}
|
||||
|
||||
# The FEOL stacks get us up to m1
|
||||
feol_stacks = [poly_stack,
|
||||
active_stack,
|
||||
li_stack]
|
||||
|
||||
# The BEOL stacks are m1 and up
|
||||
beol_stacks = [m1_stack,
|
||||
m2_stack,
|
||||
m3_stack,
|
||||
m4_stack]
|
||||
|
||||
layer_stacks = feol_stacks + beol_stacks
|
||||
|
||||
preferred_directions = {"poly": "V",
|
||||
"active": "V",
|
||||
"li": "V",
|
||||
"m1": "H",
|
||||
"m2": "V",
|
||||
"m3": "H",
|
||||
"m4": "V",
|
||||
"m5": "H"}
|
||||
|
||||
###################################################
|
||||
# GDS Layer Map
|
||||
###################################################
|
||||
|
||||
|
||||
layer = {}
|
||||
layer["active"] = (65, 20) # diff
|
||||
layer["activep"] = (65, 20) # diff
|
||||
layer["tap"] = (65, 44) # tap
|
||||
layer["pwellp"] = (122,16)
|
||||
layer["nwell"] = (64, 20) # nwell
|
||||
layer["dnwell"] = (64,18)
|
||||
layer["nimplant"]= (93, 44) # nsdm
|
||||
layer["pimplant"]= (94, 20) # psdm
|
||||
layer["vtl"] = (125, 44) # lvtn
|
||||
layer["vth"] = (78, 44) # hvtp (pmos only)
|
||||
layer["thkox"] = (8, 0)
|
||||
layer["poly"] = (66, 20)
|
||||
layer["contact"] = (66, 44) # licon1
|
||||
layer["npc"] = (95, 20) # npc (nitride cut)
|
||||
layer["li"] = (67, 20) # active li1
|
||||
layer["mcon"] = (67, 44) # mcon
|
||||
layer["m1"] = (68, 20) # met1
|
||||
layer["m1p"] = (68, 5) # met1 pin
|
||||
layer["via1"] = (68, 44) # via1
|
||||
layer["m2"] = (69, 20) # met2
|
||||
layer["m2p"] = (69, 5) # met2 pin
|
||||
layer["via2"] = (69, 44) # via2
|
||||
layer["m3"] = (70, 20) # met3
|
||||
layer["m3p"] = (70, 5) # met3 pin
|
||||
layer["via3"] = (70, 44) # via3
|
||||
layer["m4"] = (71, 20) # met4
|
||||
layer["m4p"] = (71, 5) # met4 pin
|
||||
layer["via4"] = (71, 44) # via4
|
||||
layer["m5"] = (72, 20) # met5
|
||||
layer["m5p"] = (72, 5) # met5 pin
|
||||
layer["boundary"]= (235, 4)
|
||||
# specific boundary type to define standard cell regions for DRC
|
||||
layer["stdc"] = (81, 4)
|
||||
layer["mem"] = (81, 2)
|
||||
# Not an official sky130 layer, but useful for router debug infos
|
||||
layer["text"]= (234, 5)
|
||||
# Excpected value according to sky130A tech file
|
||||
# If calibre is enabled, these will be swapped below
|
||||
#pin_purpose = 5
|
||||
label_purpose = 5
|
||||
#label_purpose = 16
|
||||
#pin_purpose = 16
|
||||
#label_purpose = 5
|
||||
|
||||
# pin_read purposes
|
||||
special_purposes = {layer["nwell"][0]: [layer["nwell"][1], 5, 59, 16]}
|
||||
#layer_override = {"VNB\x00": ["pwell",122]}
|
||||
layer_override = {"vnb": layer["pwellp"], "VNB": layer["pwellp"]}
|
||||
layer_override_name = {"vnb": "pwellp", "VNB": "pwellp"}
|
||||
layer_override_purpose = {122: (64, 59)}
|
||||
# Layer names for external PDKs
|
||||
layer_names = {}
|
||||
layer_names["active"] = "diff"
|
||||
layer_names["activep"] = "diff"
|
||||
layer_names["tap"] = "tap"
|
||||
layer_names["pwellp"] = "pwellp"
|
||||
layer_names["nwell"] = "nwell"
|
||||
layer_names["dnwell"] = "dnwell"
|
||||
layer_names["nimplant"]= "nsdm"
|
||||
layer_names["pimplant"]= "psdm"
|
||||
layer_names["vtl"] = "lvtn"
|
||||
layer_names["vth"] = "hvtp"
|
||||
layer_names["thkox"] = "thkox"
|
||||
layer_names["poly"] = "poly"
|
||||
layer_names["contact"] = "licon1"
|
||||
layer_names["li"] = "li1"
|
||||
layer_names["mcon"] = "mcon"
|
||||
layer_names["m1"] = "met1"
|
||||
layer_names["m1p"] = "met1"
|
||||
layer_names["via1"] = "via"
|
||||
layer_names["m2"] = "met2"
|
||||
layer_names["m2p"] = "met2"
|
||||
layer_names["via2"] = "via2"
|
||||
layer_names["m3"] = "met3"
|
||||
layer_names["m3p"] = "met3"
|
||||
layer_names["via3"] = "via3"
|
||||
layer_names["m4"] = "met4"
|
||||
layer_names["m4p"] = "met4"
|
||||
layer_names["via4"] = "via4"
|
||||
layer_names["m5p"] = "met5"
|
||||
layer_names["boundary"]= "boundary"
|
||||
layer_names["stdc"] = "areaid.standardc"
|
||||
layer_names["mem"] = "areaid.core"
|
||||
layer_names["text"] = "text"
|
||||
|
||||
|
||||
###################################################
|
||||
# DRC/LVS Rules Setup
|
||||
###################################################
|
||||
|
||||
# technology parameter
|
||||
parameter={}
|
||||
# difftap.2b
|
||||
parameter["min_tx_size"] = 0.150
|
||||
parameter["beta"] = 3
|
||||
|
||||
parameter["6T_inv_nmos_size"] = 0.205
|
||||
parameter["6T_inv_pmos_size"] = 0.09
|
||||
parameter["6T_access_size"] = 0.135
|
||||
|
||||
drc = d.design_rules("sky130")
|
||||
|
||||
# grid size
|
||||
drc["grid"] = 0.005
|
||||
|
||||
#DRC/LVS test set_up
|
||||
# Switching between calibre and magic can be useful for development,
|
||||
# it eventually should be deleted.
|
||||
NDA_PDK_ROOT = os.environ.get("NDA_PDK_ROOT", False)
|
||||
use_calibre = bool(NDA_PDK_ROOT)
|
||||
use_calibre = False
|
||||
use_klayout = False
|
||||
if use_calibre:
|
||||
# Correct order according to s8
|
||||
pin_purpose = 16
|
||||
label_purpose = 5
|
||||
|
||||
drc["drc_rules"] = NDA_PDK_ROOT + "/DRC/Calibre/s8_drcRules"
|
||||
drc["lvs_rules"] = NDA_PDK_ROOT + "/LVS/Calibre/lvs_s8_opts"
|
||||
drc["xrc_rules"] = NDA_PDK_ROOT + "/PEX/xRC/extLvsRules_s8_5lm"
|
||||
drc["layer_map"] = NDA_PDK_ROOT + "/VirtuosoOA/libs/technology_library/s8phirs_10r.layermap"
|
||||
|
||||
# minwidth_tx with contact (no dog bone transistors)
|
||||
# difftap.2b
|
||||
drc["minwidth_tx"] = 0.360
|
||||
drc["minlength_channel"] = 0.150
|
||||
|
||||
drc["pwell_to_nwell"] = 0
|
||||
# nwell.1 Minimum width of nwell/pwell
|
||||
drc.add_layer("nwell",
|
||||
width=0.840,
|
||||
spacing=1.270)
|
||||
|
||||
# poly.1a Minimum width of poly
|
||||
# poly.2 Minimum spacing of poly AND active
|
||||
drc.add_layer("poly",
|
||||
width=0.150,
|
||||
spacing=0.210)
|
||||
# poly.8
|
||||
drc["poly_extend_active"] = 0.13
|
||||
# Not a rule
|
||||
drc["poly_to_contact"] = 0
|
||||
# poly.7 Minimum enclosure of active around gate
|
||||
drc["active_enclose_gate"] = 0.075
|
||||
# poly.4 Minimum spacing of field poly to active
|
||||
drc["poly_to_active"] = 0.075
|
||||
# poly.2 Minimum spacing of field poly
|
||||
drc["poly_to_field_poly"] = 0.210
|
||||
|
||||
# difftap.1 Minimum width of active
|
||||
# difftap.3 Minimum spacing of active
|
||||
drc.add_layer("active",
|
||||
width=0.150,
|
||||
spacing=0.270)
|
||||
# difftap.8
|
||||
drc.add_enclosure("nwell",
|
||||
layer="active",
|
||||
enclosure=0.18,
|
||||
extension=0.18)
|
||||
|
||||
# nsd/psd.5a
|
||||
drc.add_enclosure("implant",
|
||||
layer="active",
|
||||
enclosure=0.125)
|
||||
|
||||
# Same as active enclosure?
|
||||
drc["implant_to_contact"] = 0.070
|
||||
# nsd/psd.1 nsd/psd.2
|
||||
drc.add_layer("implant",
|
||||
width=0.380,
|
||||
spacing=0.380,
|
||||
area=0.265)
|
||||
|
||||
# licon.1, licon.2
|
||||
drc.add_layer("contact",
|
||||
width=0.170,
|
||||
spacing=0.170)
|
||||
# licon.5c (0.06 extension), (licon.7 for extension)
|
||||
drc.add_enclosure("active",
|
||||
layer="contact",
|
||||
enclosure=0.040,
|
||||
extension=0.060)
|
||||
# licon.7
|
||||
drc["tap_extend_contact"] = 0.120
|
||||
|
||||
# licon.8 Minimum enclosure of poly around contact
|
||||
drc.add_enclosure("poly",
|
||||
layer="contact",
|
||||
enclosure=0.08,
|
||||
extension=0.08)
|
||||
# licon.11a
|
||||
drc["active_contact_to_gate"] = 0.050
|
||||
# npc.4 > licon.14 0.19 > licon.11a
|
||||
drc["poly_contact_to_gate"] = 0.270
|
||||
# licon.15
|
||||
drc["npc_enclose_poly"] = 0.1
|
||||
|
||||
# li.1, li.3
|
||||
drc.add_layer("li",
|
||||
width=0.170,
|
||||
spacing=0.170)
|
||||
|
||||
# licon.5
|
||||
drc.add_enclosure("li",
|
||||
layer="contact",
|
||||
enclosure=0,
|
||||
extension=0.080)
|
||||
|
||||
drc.add_enclosure("li",
|
||||
layer="mcon",
|
||||
enclosure=0,
|
||||
extension=0.080)
|
||||
# mcon.1, mcon.2
|
||||
drc.add_layer("mcon",
|
||||
width=0.170,
|
||||
spacing=0.210)
|
||||
|
||||
# m1.1 Minimum width of metal1
|
||||
# m1.2 Minimum spacing of metal1
|
||||
# m1.6 Minimum area of metal1
|
||||
drc.add_layer("m1",
|
||||
width=0.140,
|
||||
spacing=0.140,
|
||||
area=0.083)
|
||||
# m1.4 Minimum enclosure of metal1
|
||||
# m1.5 Minimum enclosure around contact on two opposite sides
|
||||
drc.add_enclosure("m1",
|
||||
layer="mcon",
|
||||
enclosure=0.030,
|
||||
extension=0.060)
|
||||
# via.4a Minimum enclosure around via1
|
||||
# via.5a Minimum enclosure around via1 on two opposite sides
|
||||
drc.add_enclosure("m1",
|
||||
layer="via1",
|
||||
enclosure=0.055,
|
||||
extension=0.085)
|
||||
|
||||
# via.1a Minimum width of via1
|
||||
# via.2 Minimum spacing of via1
|
||||
drc.add_layer("via1",
|
||||
width=0.150,
|
||||
spacing=0.170)
|
||||
|
||||
# m2.1 Minimum width of intermediate metal
|
||||
# m2.2 Minimum spacing of intermediate metal
|
||||
# m2.6 Minimum area of metal2
|
||||
drc.add_layer("m2",
|
||||
width=0.140,
|
||||
spacing=0.140,
|
||||
area=0.0676)
|
||||
# m2.4 Minimum enclosure around via1
|
||||
# m2.5 Minimum enclosure around via1 on two opposite sides
|
||||
drc.add_enclosure("m2",
|
||||
layer="via1",
|
||||
enclosure=0.055,
|
||||
extension=0.085)
|
||||
# via2.4 Minimum enclosure around via2
|
||||
# via2.5 Minimum enclosure around via2 on two opposite sides
|
||||
drc.add_enclosure("m2",
|
||||
layer="via2",
|
||||
enclosure=0.040,
|
||||
extension=0.085)
|
||||
|
||||
# via2.1a Minimum width of Via2
|
||||
# via2.2 Minimum spacing of Via2
|
||||
drc.add_layer("via2",
|
||||
width=0.200,
|
||||
spacing=0.200)
|
||||
|
||||
# m3.1 Minimum width of metal3
|
||||
# m3.2 Minimum spacing of metal3
|
||||
# m3.6 Minimum area of metal3
|
||||
drc.add_layer("m3",
|
||||
width=0.300,
|
||||
spacing=0.300,
|
||||
area=0.240)
|
||||
# m3.4 Minimum enclosure around via2
|
||||
drc.add_enclosure("m3",
|
||||
layer="via2",
|
||||
enclosure=0.065)
|
||||
# via3.4 Minimum enclosure around via3
|
||||
# via3.5 Minimum enclosure around via3 on two opposite sides
|
||||
drc.add_enclosure("m3",
|
||||
layer="via3",
|
||||
enclosure=0.060,
|
||||
extension=0.090)
|
||||
|
||||
# via3.1 Minimum width of Via3
|
||||
# via3.2 Minimum spacing of Via3
|
||||
drc.add_layer("via3",
|
||||
width=0.200,
|
||||
spacing=0.200)
|
||||
|
||||
# m4.1 Minimum width of metal4
|
||||
# m4.2 Minimum spacing of metal4
|
||||
# m4.7 Minimum area of metal4
|
||||
drc.add_layer("m4",
|
||||
width=0.300,
|
||||
spacing=0.300,
|
||||
area=0.240)
|
||||
# m4.3 Minimum enclosure around via3
|
||||
drc.add_enclosure("m4",
|
||||
layer="via3",
|
||||
enclosure=0.065)
|
||||
# FIXME: Wrong rule m4.3 Minimum enclosure around via3
|
||||
drc.add_enclosure("m4",
|
||||
layer="via4",
|
||||
enclosure=0.060)
|
||||
|
||||
|
||||
# via4.1 Minimum width of Via4
|
||||
# via4.2 Minimum spacing of Via4
|
||||
drc.add_layer("via4",
|
||||
width=0.800,
|
||||
spacing=0.800)
|
||||
|
||||
# FIXME: Wrong rules
|
||||
# m5.1 Minimum width of metal5
|
||||
# m5.2 Minimum spacing of metal5
|
||||
# m5.7 Minimum area of metal5
|
||||
drc.add_layer("m5",
|
||||
width=1.600,
|
||||
spacing=1.600,
|
||||
area=4.000)
|
||||
# m5.3 Minimum enclosure around via4
|
||||
drc.add_enclosure("m5",
|
||||
layer="via4",
|
||||
enclosure=0.310)
|
||||
|
||||
|
||||
|
||||
# Metal 5-10 are ommitted
|
||||
|
||||
###################################################
|
||||
# Spice Simulation Parameters
|
||||
###################################################
|
||||
|
||||
# spice info
|
||||
spice = {}
|
||||
spice["nmos"] = "sky130_fd_pr__nfet_01v8"
|
||||
spice["pmos"] = "sky130_fd_pr__pfet_01v8"
|
||||
spice["power"]="vccd1"
|
||||
spice["ground"]="vssd1"
|
||||
|
||||
# whether or not the device model is actually a subckt
|
||||
spice["device_prefix"] = "X"
|
||||
|
||||
spice["fet_libraries"] = { "TT": [[os.environ.get("SPICE_MODEL_DIR") + "/sky130.lib.spice", "tt"]],
|
||||
"SS": [[os.environ.get("SPICE_MODEL_DIR") + "/sky130.lib.spice", "ss"]],
|
||||
"FF": [[os.environ.get("SPICE_MODEL_DIR") + "/sky130.lib.spice", "ff"]],
|
||||
"SF": [[os.environ.get("SPICE_MODEL_DIR") + "/sky130.lib.spice", "sf"]],
|
||||
"FS": [[os.environ.get("SPICE_MODEL_DIR") + "/sky130.lib.spice", "fs"]] }
|
||||
|
||||
# spice stimulus related variables
|
||||
spice["feasible_period"] = 10 # estimated feasible period in ns
|
||||
spice["supply_voltages"] = [1.7, 1.8, 1.9] # Supply voltage corners in [Volts]
|
||||
spice["nom_supply_voltage"] = 1.8 # Nominal supply voltage in [Volts]
|
||||
spice["rise_time"] = 0.005 # rise time in [Nano-seconds]
|
||||
spice["fall_time"] = 0.005 # fall time in [Nano-seconds]
|
||||
spice["temperatures"] = [0, 25, 100] # Temperature corners (celcius)
|
||||
spice["nom_temperature"] = 25 # Nominal temperature (celcius)
|
||||
|
||||
# analytical delay parameters
|
||||
spice["nom_threshold"] = 0.49 # Typical Threshold voltage in Volts
|
||||
spice["wire_unit_r"] = 0.125 # Unit wire resistance in ohms/square
|
||||
spice["wire_unit_c"] = 0.134 # Unit wire capacitance ff/um^2
|
||||
spice["min_tx_drain_c"] = 0.7 # Minimum transistor drain capacitance in ff
|
||||
spice["min_tx_gate_c"] = 0.2 # Minimum transistor gate capacitance in ff
|
||||
spice["dff_setup"] = 102.5391 # DFF setup time in ps
|
||||
spice["dff_hold"] = -56 # DFF hold time in ps
|
||||
spice["dff_in_cap"] = 6.89 # Input capacitance (D) [Femto-farad]
|
||||
spice["dff_out_cap"] = 6.89 # Output capacitance (Q) [Femto-farad]
|
||||
|
||||
# analytical power parameters, many values are temporary
|
||||
spice["bitcell_leakage"] = 1 # Leakage power of a single bitcell in nW
|
||||
spice["inv_leakage"] = 1 # Leakage power of inverter in nW
|
||||
spice["nand2_leakage"] = 1 # Leakage power of 2-input nand in nW
|
||||
spice["nand3_leakage"] = 1 # Leakage power of 3-input nand in nW
|
||||
spice["nand4_leakage"] = 1 # Leakage power of 4-input nand in nW
|
||||
spice["nor2_leakage"] = 1 # Leakage power of 2-input nor in nW
|
||||
spice["dff_leakage"] = 1 # Leakage power of flop in nW
|
||||
|
||||
spice["default_event_frequency"] = 100 # Default event activity of every gate. MHz
|
||||
|
||||
# Parameters related to sense amp enable timing and delay chain/RBL sizing
|
||||
parameter["le_tau"] = 2.25 # In pico-seconds.
|
||||
parameter["cap_relative_per_ff"] = 7.5 # Units of Relative Capacitance/ Femto-Farad
|
||||
parameter["dff_clk_cin"] = 30.6 # relative capacitance
|
||||
parameter["6tcell_wl_cin"] = 3 # relative capacitance
|
||||
parameter["min_inv_para_delay"] = 2.4 # Tau delay units
|
||||
parameter["sa_en_pmos_size"] = 0.72 # micro-meters
|
||||
parameter["sa_en_nmos_size"] = 0.27 # micro-meters
|
||||
parameter["sa_inv_pmos_size"] = 0.54 # micro-meters
|
||||
parameter["sa_inv_nmos_size"] = 0.27 # micro-meters
|
||||
parameter["bitcell_drain_cap"] = 0.1 # In Femto-Farad, approximation of drain capacitance
|
||||
|
||||
###################################################
|
||||
# Technology Tool Preferences
|
||||
###################################################
|
||||
|
||||
if use_calibre:
|
||||
drc_name = "calibre"
|
||||
lvs_name = "calibre"
|
||||
pex_name = "calibre"
|
||||
elif use_klayout:
|
||||
drc_name = "klayout"
|
||||
lvs_name = "klayout"
|
||||
pex_name = "klayout"
|
||||
else:
|
||||
drc_name = "magic"
|
||||
lvs_name = "netgen"
|
||||
pex_name = "magic"
|
||||
|
||||
|
||||
# This is used by uniqify to not rename the library cells
|
||||
library_prefix_name = "sky130_fd_bd_sram__"
|
||||
# List of cells to skip running DRC/LVS on directly
|
||||
# This will look for a maglef file and copy it over the mag file
|
||||
# before DRC after extraction
|
||||
|
||||
# gds flatglob sky130_fd_bd_sram__openram_sp_cell_opt1a_cell
|
||||
# gds flatglob sky130_fd_bd_sram__openram_sp_cell_opt1a_replica_ce
|
||||
# gds flatglob sky130_fd_bd_sram__openram_sp_cell_opt1_replica_cell
|
||||
# gds flatglob sky130_fd_bd_sram__openram_sp_cell_opt1_replica_ce
|
||||
# gds flatglob sky130_fd_bd_sram__openram_sp_cell_opt1_replica_cell
|
||||
# gds flatglob sky130_fd_bd_sram__openram_sp_cell_opt1a_cell
|
||||
# gds flatglob sky130_fd_bd_sram__sram_sp_cell_fom_serifs
|
||||
|
||||
flatglob = ["*_?mos_m*",
|
||||
"sky130_fd_bd_sram__sram_sp_cell_fom_serifs",
|
||||
|
||||
"sky130_fd_bd_sram__sram_sp_cell",
|
||||
"sky130_fd_bd_sram__openram_sp_cell_opt1_replica_cell",
|
||||
"sky130_fd_bd_sram__openram_sp_cell_opt1a_replica_cell",
|
||||
|
||||
"sky130_fd_bd_sram__sram_sp_cell_opt1_ce",
|
||||
"sky130_fd_bd_sram__openram_sp_cell_opt1_replica_ce",
|
||||
"sky130_fd_bd_sram__openram_sp_cell_opt1a_replica_ce",
|
||||
"sky130_fd_bd_sram__sram_sp_wlstrap_ce",
|
||||
"sky130_fd_bd_sram__sram_sp_wlstrap_p_ce"]
|
||||
|
||||
blackbox_cells = ["sky130_fd_bd_sram__openram_dp_cell",
|
||||
"sky130_fd_bd_sram__openram_dp_cell_dummy",
|
||||
"sky130_fd_bd_sram__openram_dp_cell_replica",
|
||||
|
||||
"sky130_fd_bd_sram__openram_sp_cell_opt1_noblcon",
|
||||
"sky130_fd_bd_sram__openram_sp_cell_opt1a_noblcon",
|
||||
"sky130_fd_bd_sram__openram_sp_colend_replica",
|
||||
"sky130_fd_bd_sram__openram_sp_colenda_replica",
|
||||
"sky130_fd_bd_sram__sram_sp_cell_opt1a",
|
||||
"sky130_fd_bd_sram__openram_sp_cell_opt1a_dummy",
|
||||
"sky130_fd_bd_sram__openram_sp_cell_opt1_dummy",
|
||||
"sky130_fd_bd_sram__sram_sp_cell_opt1_ce",
|
||||
"sky130_fd_bd_sram__sram_sp_cell_opt1",
|
||||
"sky130_fd_bd_sram__openram_sp_cell_opt1_replica",
|
||||
"sky130_fd_bd_sram__openram_sp_cell_opt1a_replica",
|
||||
"sky130_fd_bd_sram__sram_sp_colend",
|
||||
"sky130_fd_bd_sram__sram_sp_colend_cent",
|
||||
"sky130_fd_bd_sram__sram_sp_colend_p_cent",
|
||||
"sky130_fd_bd_sram__sram_sp_colenda",
|
||||
"sky130_fd_bd_sram__sram_sp_colenda_cent",
|
||||
"sky130_fd_bd_sram__sram_sp_colenda_p_cent",
|
||||
"sky130_fd_bd_sram__sram_sp_rowend",
|
||||
"sky130_fd_bd_sram__sram_sp_rowenda",
|
||||
"sky130_fd_bd_sram__openram_sp_rowend_replica",
|
||||
"sky130_fd_bd_sram__openram_sp_rowenda_replica",
|
||||
"sky130_fd_bd_sram__sram_sp_corner",
|
||||
"sky130_fd_bd_sram__sram_sp_cornera",
|
||||
"sky130_fd_bd_sram__sram_sp_cornerb",
|
||||
"sky130_fd_bd_sram__sram_sp_wlstrapa",
|
||||
"sky130_fd_bd_sram__sram_sp_wlstrap_ce",
|
||||
"sky130_fd_bd_sram__sram_sp_wlstrap",
|
||||
"sky130_fd_bd_sram__sram_sp_wlstrap_p_ce",
|
||||
"sky130_fd_bd_sram__sram_sp_wlstrap_p"]
|
||||
@@ -0,0 +1,849 @@
|
||||
#!/usr/bin/env python3
|
||||
# See LICENSE for licensing information.
|
||||
#
|
||||
# Copyright (c) 2016-2023 Regents of the University of California
|
||||
# All rights reserved.
|
||||
#
|
||||
|
||||
|
||||
import os
|
||||
from openram import drc as d
|
||||
|
||||
"""
|
||||
File containing the process technology parameters for Skywater 130nm.
|
||||
"""
|
||||
|
||||
###################################################
|
||||
# Custom modules
|
||||
###################################################
|
||||
|
||||
# This uses the default classes to instantiate module from
|
||||
# '$OPENRAM_HOME/compiler/modules'.
|
||||
# Using tech_modules['cellname'] you can override each class by providing a custom
|
||||
# implementation in '$OPENRAM_TECHDIR/modules/'
|
||||
# For example: tech_modules["contact"] = "contact_freepdk45"
|
||||
tech_modules = d.module_type()
|
||||
|
||||
# These modules have been hand designed and provided in this repository.
|
||||
tech_modules["nand2_dec"] = "nand2_dec"
|
||||
tech_modules["nand3_dec"] = "nand3_dec"
|
||||
tech_modules["nand4_dec"] = "nand4_dec"
|
||||
|
||||
# Override default OpenRAM modules to sky130 modules
|
||||
# These are for single port and dual port as a list,
|
||||
# or for both if there is no list,
|
||||
# or only applicable to one if there is no list.
|
||||
tech_modules["bitcell_1port"] = "sky130_bitcell"
|
||||
tech_modules["replica_bitcell_1port"] = "sky130_replica_bitcell"
|
||||
tech_modules["dummy_bitcell_1port"] = "sky130_dummy_bitcell"
|
||||
|
||||
tech_modules["replica_bitcell_2port"] = "replica_bitcell_2port"
|
||||
tech_modules["dummy_bitcell_2port"] = "dummy_bitcell_2port"
|
||||
tech_modules["bitcell_2port"] = "bitcell_2port"
|
||||
|
||||
tech_modules["bitcell_array"] = ["sky130_bitcell_array", "bitcell_array"]
|
||||
tech_modules["replica_bitcell_array"] = ["sky130_replica_bitcell_array", "replica_bitcell_array"]
|
||||
tech_modules["capped_replica_bitcell_array"] = ["sky130_capped_replica_bitcell_array", "capped_replica_bitcell_array"]
|
||||
tech_modules["dummy_array"] = ["sky130_dummy_array", "dummy_array"]
|
||||
|
||||
tech_modules["replica_column"] = ["sky130_replica_column", "replica_column"]
|
||||
|
||||
tech_modules["col_cap_array"] = ["sky130_col_cap_array", "col_cap_array"]
|
||||
tech_modules["col_cap"] = ["sky130_col_cap", "col_cap_bitcell_2port"]
|
||||
tech_modules["corner"] = ["sky130_corner", None]
|
||||
tech_modules["internal"] = ["sky130_internal", None]
|
||||
tech_modules["row_cap_array"] = ["sky130_row_cap_array", "row_cap_array"]
|
||||
tech_modules["row_cap"] = ["sky130_row_cap", "row_cap_bitcell_2port"]
|
||||
|
||||
# These modules are auto-generated from the nand decoders above and are not
|
||||
# found in this.
|
||||
tech_modules["buf_dec"] = "pbuf_dec"
|
||||
tech_modules["inv_dec"] = "pinv_dec"
|
||||
tech_modules["and2_dec"] = "and2_dec"
|
||||
tech_modules["and3_dec"] = "and3_dec"
|
||||
tech_modules["and4_dec"] = "and4_dec"
|
||||
|
||||
###################################################
|
||||
# Custom cell properties
|
||||
###################################################
|
||||
cell_properties = d.cell_properties()
|
||||
|
||||
cell_properties.bitcell_power_pin_directions = ("H", "H")
|
||||
|
||||
cell_properties.bitcell_1port.mirror.x = True
|
||||
cell_properties.bitcell_1port.mirror.y = True
|
||||
cell_properties.bitcell_1port.end_caps = True
|
||||
cell_properties.bitcell_1port.has_corners = True
|
||||
cell_properties.bitcell_1port.boundary_layer = "mem"
|
||||
cell_properties.bitcell_1port.port_order = ['bl', 'br', 'gnd', 'vdd', 'vpb', 'vnb', 'wl']
|
||||
cell_properties.bitcell_1port.port_types = ["OUTPUT", "OUTPUT", "GROUND", "POWER", "BIAS", "BIAS", "INPUT"]
|
||||
cell_properties.bitcell_1port.port_map = {'bl': 'BL',
|
||||
'br': 'BR',
|
||||
'wl': 'WL',
|
||||
'vdd': 'VPWR',
|
||||
'vnb': 'VNB',
|
||||
'vpb': 'VPB',
|
||||
'gnd': 'VGND'}
|
||||
|
||||
cell_properties.bitcell_1port.wl_layer = "m2"
|
||||
cell_properties.bitcell_1port.bl_layer = "m1"
|
||||
cell_properties.bitcell_1port.vdd_layer = "m1"
|
||||
cell_properties.bitcell_1port.vdd_dir = "V"
|
||||
cell_properties.bitcell_1port.gnd_layer = "m2"
|
||||
cell_properties.bitcell_1port.gnd_dir = "H"
|
||||
|
||||
cell_properties.bitcell_2port.mirror.x = True
|
||||
cell_properties.bitcell_2port.mirror.y = True
|
||||
cell_properties.bitcell_2port.end_caps = True
|
||||
cell_properties.bitcell_2port.has_corners = False
|
||||
cell_properties.bitcell_2port.port_order = ['bl0', 'br0', 'bl1', 'br1', 'wl0', 'wl1', 'vdd', 'gnd']
|
||||
cell_properties.bitcell_2port.port_map = {'bl0': 'BL0',
|
||||
'br0': 'BR0',
|
||||
'bl1': 'BL1',
|
||||
'br1': 'BR1',
|
||||
'wl0': 'WL0',
|
||||
'wl1': 'WL1',
|
||||
'vdd': 'VDD',
|
||||
'gnd': 'GND'}
|
||||
cell_properties.bitcell_1port.wl_layer = "m2"
|
||||
cell_properties.bitcell_1port.vdd_layer = "m2"
|
||||
cell_properties.bitcell_1port.vdd_dir = "H"
|
||||
cell_properties.bitcell_1port.gnd_layer = "m2"
|
||||
cell_properties.bitcell_1port.gnd_dir = "H"
|
||||
cell_properties.bitcell_2port.wl_layer = "m2"
|
||||
cell_properties.bitcell_2port.vdd_layer = "m1"
|
||||
cell_properties.bitcell_2port.vdd_dir = "H"
|
||||
cell_properties.bitcell_2port.gnd_layer = "m2"
|
||||
cell_properties.bitcell_2port.gnd_dir = "H"
|
||||
|
||||
cell_properties.col_cap_1port_bitcell = d.cell(['bl', 'br', 'vdd', 'gnd', 'vpb', 'vnb', 'gate'],
|
||||
['INPUT', 'INPUT','POWER', 'GROUND', 'BIAS', 'BIAS', 'INPUT'],
|
||||
{'bl': 'bl',
|
||||
'br': 'br',
|
||||
'vdd': 'vdd',
|
||||
'gnd': 'gnd',
|
||||
'vnb': 'vnb',
|
||||
'vpb': 'vpb',
|
||||
'gate': 'gate'})
|
||||
cell_properties.col_cap_1port_bitcell.boundary_layer = "mem"
|
||||
|
||||
cell_properties.col_cap_1port_strap_power = d.cell(['vdd', 'vpb', 'vnb'],
|
||||
['POWER', 'BIAS', 'BIAS'],
|
||||
{'vnb': 'VNB',
|
||||
'vpb': 'VPB',
|
||||
'vdd': 'VPWR'})
|
||||
cell_properties.col_cap_1port_strap_power.boundary_layer = "mem"
|
||||
|
||||
cell_properties.col_cap_1port_strap_ground = d.cell(['gnd', 'vpb', 'vnb'],
|
||||
['GROUND', 'BIAS', 'BIAS'],
|
||||
{'vnb': 'VNB',
|
||||
'vpb': 'VPB',
|
||||
'gnd': 'VGND'})
|
||||
cell_properties.col_cap_1port_strap_ground.boundary_layer = "mem"
|
||||
|
||||
cell_properties.row_cap_1port_cell = d.cell(['vdd', 'wl'],
|
||||
['POWER', 'INPUT'],
|
||||
{'wl': 'WL',
|
||||
'vdd': 'VPWR'})
|
||||
cell_properties.row_cap_1port_cell.boundary_layer = "mem"
|
||||
|
||||
cell_properties.col_cap_2port.port_order = ['bl0', 'br0', 'bl1', 'br1', 'vdd']
|
||||
cell_properties.col_cap_2port.port_map = {'bl0': 'BL0',
|
||||
'br0': 'BR0',
|
||||
'bl1': 'BL1',
|
||||
'br1': 'BR1',
|
||||
'vdd': 'VDD'}
|
||||
|
||||
cell_properties.row_cap_2port.port_order = ['wl0', 'wl1', 'gnd']
|
||||
cell_properties.row_cap_2port.port_map = {'wl0': 'WL0',
|
||||
'wl1': 'WL1',
|
||||
'gnd': 'GND'}
|
||||
|
||||
|
||||
cell_properties.ptx.bin_spice_models = True
|
||||
cell_properties.ptx.model_is_subckt = True
|
||||
|
||||
cell_properties.pgate.add_implants = True
|
||||
|
||||
cell_properties.use_strap = True
|
||||
cell_properties.strap_module = "internal"
|
||||
cell_properties.strap_version = "wlstrap"
|
||||
|
||||
cell_properties.dff.port_order = ['D', 'Q', 'clk', 'vdd', 'gnd']
|
||||
cell_properties.dff.port_map = {'D': 'D',
|
||||
'Q': 'Q',
|
||||
'clk': 'CLK',
|
||||
'vdd': 'VDD',
|
||||
'gnd': 'GND'}
|
||||
|
||||
cell_properties.nand2_dec.port_order = ['A', 'B', 'Z', 'vdd', 'gnd']
|
||||
cell_properties.nand2_dec.port_map = {'A': 'A',
|
||||
'B': 'B',
|
||||
'Z': 'Z',
|
||||
'vdd': 'VDD',
|
||||
'gnd': 'GND'}
|
||||
|
||||
cell_properties.nand3_dec.port_order = ['A', 'B', 'C', 'Z', 'vdd', 'gnd']
|
||||
cell_properties.nand3_dec.port_map = {'A': 'A',
|
||||
'B': 'B',
|
||||
'C': 'C',
|
||||
'Z': 'Z',
|
||||
'vdd': 'VDD',
|
||||
'gnd': 'GND'}
|
||||
|
||||
cell_properties.nand4_dec.port_order = ['A', 'B', 'C', 'D', 'Z', 'vdd', 'gnd']
|
||||
cell_properties.nand4_dec.port_map = {'A': 'A',
|
||||
'B': 'B',
|
||||
'C': 'C',
|
||||
'D': 'D',
|
||||
'Z': 'Z',
|
||||
'vdd': 'VDD',
|
||||
'gnd': 'GND'}
|
||||
|
||||
cell_properties.sense_amp.port_order = ['bl', 'br', 'dout', 'en', 'vdd', 'gnd']
|
||||
cell_properties.sense_amp.port_map = {'bl': 'BL',
|
||||
'br': 'BR',
|
||||
'dout': 'DOUT',
|
||||
'en': 'EN',
|
||||
'vdd': 'VDD',
|
||||
'gnd': 'GND'}
|
||||
|
||||
cell_properties.write_driver.port_order = ['din', 'bl', 'br', 'en', 'vdd', 'gnd']
|
||||
cell_properties.write_driver.port_map = {'din': 'DIN',
|
||||
'bl': 'BL',
|
||||
'br': 'BR',
|
||||
'en': 'EN',
|
||||
'vdd': 'VDD',
|
||||
'gnd': 'GND'}
|
||||
|
||||
|
||||
# You can override the GDS for custom cell using the following:
|
||||
# If it is a list, the first is single port and the second is dual port.
|
||||
# If it is string, it is used for both single and dual port.
|
||||
cell_properties.names["dff"] = "sky130_fd_bd_sram__openram_dff"
|
||||
cell_properties.names["nand2_dec"] = ["sky130_fd_bd_sram__openram_sp_nand2_dec", "sky130_fd_bd_sram__openram_dp_nand2_dec"]
|
||||
cell_properties.names["nand3_dec"] = ["sky130_fd_bd_sram__openram_sp_nand3_dec", "sky130_fd_bd_sram__openram_dp_nand3_dec"]
|
||||
cell_properties.names["nand4_dec"] = ["sky130_fd_bd_sram__openram_sp_nand4_dec", "sky130_fd_bd_sram__openram_dp_nand4_dec"]
|
||||
|
||||
cell_properties.names["bitcell_2port"] = "sky130_fd_bd_sram__openram_dp_cell"
|
||||
cell_properties.names["dummy_bitcell_2port"] = "sky130_fd_bd_sram__openram_dp_cell_dummy"
|
||||
cell_properties.names["replica_bitcell_2port"] = "sky130_fd_bd_sram__openram_dp_cell_replica"
|
||||
cell_properties.names["col_cap_bitcell_2port"] = "sky130_fd_bd_sram__openram_dp_cell_cap_col"
|
||||
cell_properties.names["row_cap_bitcell_2port"] = "sky130_fd_bd_sram__openram_dp_cell_cap_row"
|
||||
cell_properties.names["sense_amp"] = "sky130_fd_bd_sram__openram_sense_amp"
|
||||
cell_properties.names["write_driver"] = "sky130_fd_bd_sram__openram_write_driver"
|
||||
|
||||
array_row_multiple = 2
|
||||
array_col_multiple = 2
|
||||
|
||||
###################################################
|
||||
# Custom layer properties
|
||||
###################################################
|
||||
layer_properties = d.layer_properties()
|
||||
layer_properties.hierarchical_decoder.bus_layer = "m1"
|
||||
layer_properties.hierarchical_decoder.bus_directions = "nonpref"
|
||||
layer_properties.hierarchical_decoder.input_layer = "li"
|
||||
layer_properties.hierarchical_decoder.output_layer = "m2"
|
||||
layer_properties.hierarchical_decoder.vertical_supply = True
|
||||
|
||||
layer_properties.hierarchical_predecode.bus_layer = "m1"
|
||||
layer_properties.hierarchical_predecode.bus_directions = "nonpref"
|
||||
# This is added to allow the column decoder connections on m2
|
||||
layer_properties.hierarchical_predecode.bus_pitch_factor = 1.2
|
||||
layer_properties.hierarchical_predecode.bus_space_factor = 1.5
|
||||
layer_properties.hierarchical_predecode.input_layer = "li"
|
||||
layer_properties.hierarchical_predecode.output_layer = "m2"
|
||||
layer_properties.hierarchical_predecode.vertical_supply = True
|
||||
layer_properties.hierarchical_predecode.force_horizontal_input_contact = True
|
||||
|
||||
layer_properties.bank.stack = "m2_stack"
|
||||
layer_properties.bank.pitch = "m3_pitch"
|
||||
|
||||
layer_properties.column_mux_array.select_layer = "m3"
|
||||
layer_properties.column_mux_array.bitline_layer = "m1"
|
||||
|
||||
layer_properties.port_address.supply_offset = True
|
||||
|
||||
layer_properties.port_data.enable_layer = "m1"
|
||||
layer_properties.port_data.channel_route_bitlines = False
|
||||
|
||||
layer_properties.replica_column.even_rows = True
|
||||
|
||||
layer_properties.wordline_driver.vertical_supply = True
|
||||
|
||||
layer_properties.global_wordline_layer = "m5"
|
||||
|
||||
|
||||
###################################################
|
||||
# Discrete tx bins
|
||||
###################################################
|
||||
# enforce that tx sizes are within 25% of requested size after fingering.
|
||||
accuracy_requirement = 0.75
|
||||
nmos_bins = {
|
||||
0.15 : [0.36, 0.39, 0.42, 0.52, 0.54, 0.55, 0.58, 0.6, 0.61, 0.64, 0.65, 0.74, 0.84, 1.0, 1.26, 1.68, 2.0, 3.0, 5.0, 7.0],
|
||||
0.18 : [0.42, 0.65, 1.0, 3.0, 5.0, 7.0],
|
||||
0.25 : [0.65, 1.0, 3.0, 5.0, 7.0],
|
||||
0.5 : [0.42, 0.55, 0.65, 1.0, 3.0, 5.0, 7.0],
|
||||
1.0 : [0.42, 0.65, 1.0, 3.0, 5.0, 7.0],
|
||||
2.0 : [0.42, 0.65, 1.0, 3.0, 5.0, 7.0],
|
||||
4.0 : [0.42, 0.65, 1.0, 3.0, 5.0, 7.0],
|
||||
8.0 : [0.42, 0.65, 1.0, 3.0, 5.0, 7.0],
|
||||
20.0 : [0.42, 0.65, 1.0, 3.0, 5.0, 7.0]
|
||||
}
|
||||
|
||||
pmos_bins = {
|
||||
0.15 : [0.42, 0.55, 0.64, 0.84, 1.0, 1.12, 1.26, 1.65, 1.68, 2.0, 3.0, 5.0, 7.0],
|
||||
1.0 : [0.42, 0.55, 1.0, 3.0, 5.0, 7.0],
|
||||
2.0 : [0.42, 0.55, 1.0, 3.0, 5.0, 7.0],
|
||||
4.0 : [0.42, 0.55, 1.0, 3.0, 5.0, 7.0],
|
||||
8.0 : [0.42, 0.55, 1.0, 3.0, 5.0, 7.0],
|
||||
0.17 : [0.42, 0.55, 0.64, 0.84, 1.0, 1.12],
|
||||
0.18 : [0.42, 0.55, 0.64, 0.84, 1.0, 1.12, 1.26, 1.68, 2.0, 3.0, 5.0, 7.0],
|
||||
0.25 : [1.0, 3.0, 5.0, 7.0],
|
||||
0.5 : [0.42, 0.55, 1.0, 3.0, 5.0, 7.0],
|
||||
20.0 : [0.42]
|
||||
}
|
||||
###################################################
|
||||
# GDS file info
|
||||
###################################################
|
||||
GDS = {}
|
||||
# gds units
|
||||
# From http://www.cnf.cornell.edu/cnf_spie9.html: "The first
|
||||
# is the size of a database unit in user units. The second is the size
|
||||
# of a database unit in meters. For example, if your library was
|
||||
# created with the default units (user unit = 1 um and 1000 database
|
||||
# units per user unit), then the first number would be 0.001 and the
|
||||
# second number would be 10-9. Typically, the first number is less than
|
||||
# 1, since you use more than 1 database unit per user unit. To
|
||||
# calculate the size of a user unit in meters, divide the second number
|
||||
# by the first."
|
||||
GDS["unit"] = (0.001, 1e-9)
|
||||
#GDS["unit"]=(0.001, 1e-6)
|
||||
|
||||
###################################################
|
||||
# Interconnect stacks
|
||||
###################################################
|
||||
|
||||
poly_stack = ("poly", "contact", "li")
|
||||
active_stack = ("active", "contact", "li")
|
||||
li_stack = ("li", "mcon", "m1")
|
||||
m1_stack = ("m1", "via1", "m2")
|
||||
m2_stack = ("m2", "via2", "m3")
|
||||
m3_stack = ("m3", "via3", "m4")
|
||||
m4_stack = ("m4", "via4", "m5")
|
||||
|
||||
lef_rom_interconnect = ["m1", "m2", "m3", "m4"]
|
||||
|
||||
layer_indices = {"poly": 0,
|
||||
"active": 0,
|
||||
"nwell": 0,
|
||||
"li": 1,
|
||||
"m1": 2,
|
||||
"m2": 3,
|
||||
"m3": 4,
|
||||
"m4": 5,
|
||||
"m5": 6}
|
||||
|
||||
# The FEOL stacks get us up to m1
|
||||
feol_stacks = [poly_stack,
|
||||
active_stack,
|
||||
li_stack]
|
||||
|
||||
# The BEOL stacks are m1 and up
|
||||
beol_stacks = [m1_stack,
|
||||
m2_stack,
|
||||
m3_stack,
|
||||
m4_stack]
|
||||
|
||||
layer_stacks = feol_stacks + beol_stacks
|
||||
|
||||
preferred_directions = {"poly": "V",
|
||||
"active": "V",
|
||||
"li": "V",
|
||||
"m1": "H",
|
||||
"m2": "V",
|
||||
"m3": "H",
|
||||
"m4": "V",
|
||||
"m5": "H"}
|
||||
|
||||
###################################################
|
||||
# GDS Layer Map
|
||||
###################################################
|
||||
|
||||
|
||||
layer = {}
|
||||
layer["active"] = (65, 20) # diff
|
||||
layer["activep"] = (65, 20) # diff
|
||||
layer["tap"] = (65, 44) # tap
|
||||
layer["pwellp"] = (122,16)
|
||||
layer["nwell"] = (64, 20) # nwell
|
||||
layer["dnwell"] = (64,18)
|
||||
layer["nimplant"]= (93, 44) # nsdm
|
||||
layer["pimplant"]= (94, 20) # psdm
|
||||
layer["vtl"] = (125, 44) # lvtn
|
||||
layer["vth"] = (78, 44) # hvtp (pmos only)
|
||||
layer["thkox"] = (8, 0)
|
||||
layer["poly"] = (66, 20)
|
||||
layer["contact"] = (66, 44) # licon1
|
||||
layer["npc"] = (95, 20) # npc (nitride cut)
|
||||
layer["li"] = (67, 20) # active li1
|
||||
layer["mcon"] = (67, 44) # mcon
|
||||
layer["m1"] = (68, 20) # met1
|
||||
layer["m1p"] = (68, 5) # met1 pin
|
||||
layer["via1"] = (68, 44) # via1
|
||||
layer["m2"] = (69, 20) # met2
|
||||
layer["m2p"] = (69, 5) # met2 pin
|
||||
layer["via2"] = (69, 44) # via2
|
||||
layer["m3"] = (70, 20) # met3
|
||||
layer["m3p"] = (70, 5) # met3 pin
|
||||
layer["via3"] = (70, 44) # via3
|
||||
layer["m4"] = (71, 20) # met4
|
||||
layer["m4p"] = (71, 5) # met4 pin
|
||||
layer["via4"] = (71, 44) # via4
|
||||
layer["m5"] = (72, 20) # met5
|
||||
layer["m5p"] = (72, 5) # met5 pin
|
||||
layer["boundary"]= (235, 4)
|
||||
# specific boundary type to define standard cell regions for DRC
|
||||
layer["stdc"] = (81, 4)
|
||||
layer["mem"] = (81, 2)
|
||||
# Not an official sky130 layer, but useful for router debug infos
|
||||
layer["text"]= (234, 5)
|
||||
# Excpected value according to sky130A tech file
|
||||
# If calibre is enabled, these will be swapped below
|
||||
#pin_purpose = 5
|
||||
label_purpose = 5
|
||||
#label_purpose = 16
|
||||
#pin_purpose = 16
|
||||
#label_purpose = 5
|
||||
|
||||
# pin_read purposes
|
||||
special_purposes = {layer["nwell"][0]: [layer["nwell"][1], 5, 59, 16]}
|
||||
#layer_override = {"VNB\x00": ["pwell",122]}
|
||||
layer_override = {"vnb": layer["pwellp"], "VNB": layer["pwellp"]}
|
||||
layer_override_name = {"vnb": "pwellp", "VNB": "pwellp"}
|
||||
layer_override_purpose = {122: (64, 59)}
|
||||
# Layer names for external PDKs
|
||||
layer_names = {}
|
||||
layer_names["active"] = "diff"
|
||||
layer_names["activep"] = "diff"
|
||||
layer_names["tap"] = "tap"
|
||||
layer_names["pwellp"] = "pwellp"
|
||||
layer_names["nwell"] = "nwell"
|
||||
layer_names["dnwell"] = "dnwell"
|
||||
layer_names["nimplant"]= "nsdm"
|
||||
layer_names["pimplant"]= "psdm"
|
||||
layer_names["vtl"] = "lvtn"
|
||||
layer_names["vth"] = "hvtp"
|
||||
layer_names["thkox"] = "thkox"
|
||||
layer_names["poly"] = "poly"
|
||||
layer_names["contact"] = "licon1"
|
||||
layer_names["li"] = "li1"
|
||||
layer_names["mcon"] = "mcon"
|
||||
layer_names["m1"] = "met1"
|
||||
layer_names["m1p"] = "met1"
|
||||
layer_names["via1"] = "via"
|
||||
layer_names["m2"] = "met2"
|
||||
layer_names["m2p"] = "met2"
|
||||
layer_names["via2"] = "via2"
|
||||
layer_names["m3"] = "met3"
|
||||
layer_names["m3p"] = "met3"
|
||||
layer_names["via3"] = "via3"
|
||||
layer_names["m4"] = "met4"
|
||||
layer_names["m4p"] = "met4"
|
||||
layer_names["via4"] = "via4"
|
||||
layer_names["m5p"] = "met5"
|
||||
layer_names["boundary"]= "boundary"
|
||||
layer_names["stdc"] = "areaid.standardc"
|
||||
layer_names["mem"] = "areaid.core"
|
||||
layer_names["text"] = "text"
|
||||
|
||||
|
||||
###################################################
|
||||
# DRC/LVS Rules Setup
|
||||
###################################################
|
||||
|
||||
# technology parameter
|
||||
parameter={}
|
||||
# difftap.2b
|
||||
parameter["min_tx_size"] = 0.150
|
||||
parameter["beta"] = 3
|
||||
|
||||
parameter["6T_inv_nmos_size"] = 0.205
|
||||
parameter["6T_inv_pmos_size"] = 0.09
|
||||
parameter["6T_access_size"] = 0.135
|
||||
|
||||
drc = d.design_rules("sky130")
|
||||
|
||||
# grid size
|
||||
drc["grid"] = 0.005
|
||||
|
||||
#DRC/LVS test set_up
|
||||
# Switching between calibre and magic can be useful for development,
|
||||
# it eventually should be deleted.
|
||||
NDA_PDK_ROOT = os.environ.get("NDA_PDK_ROOT", False)
|
||||
use_calibre = bool(NDA_PDK_ROOT)
|
||||
use_calibre = False
|
||||
use_klayout = False
|
||||
if use_calibre:
|
||||
# Correct order according to s8
|
||||
pin_purpose = 16
|
||||
label_purpose = 5
|
||||
|
||||
drc["drc_rules"] = NDA_PDK_ROOT + "/DRC/Calibre/s8_drcRules"
|
||||
drc["lvs_rules"] = NDA_PDK_ROOT + "/LVS/Calibre/lvs_s8_opts"
|
||||
drc["xrc_rules"] = NDA_PDK_ROOT + "/PEX/xRC/extLvsRules_s8_5lm"
|
||||
drc["layer_map"] = NDA_PDK_ROOT + "/VirtuosoOA/libs/technology_library/s8phirs_10r.layermap"
|
||||
|
||||
# minwidth_tx with contact (no dog bone transistors)
|
||||
# difftap.2b
|
||||
drc["minwidth_tx"] = 0.360
|
||||
drc["minlength_channel"] = 0.150
|
||||
|
||||
drc["pwell_to_nwell"] = 0
|
||||
# nwell.1 Minimum width of nwell/pwell
|
||||
drc.add_layer("nwell",
|
||||
width=0.840,
|
||||
spacing=1.270)
|
||||
|
||||
# poly.1a Minimum width of poly
|
||||
# poly.2 Minimum spacing of poly AND active
|
||||
drc.add_layer("poly",
|
||||
width=0.150,
|
||||
spacing=0.210)
|
||||
# poly.8
|
||||
drc["poly_extend_active"] = 0.13
|
||||
# Not a rule
|
||||
drc["poly_to_contact"] = 0
|
||||
# poly.7 Minimum enclosure of active around gate
|
||||
drc["active_enclose_gate"] = 0.075
|
||||
# poly.4 Minimum spacing of field poly to active
|
||||
drc["poly_to_active"] = 0.075
|
||||
# poly.2 Minimum spacing of field poly
|
||||
drc["poly_to_field_poly"] = 0.210
|
||||
|
||||
# difftap.1 Minimum width of active
|
||||
# difftap.3 Minimum spacing of active
|
||||
drc.add_layer("active",
|
||||
width=0.150,
|
||||
spacing=0.270)
|
||||
# difftap.8
|
||||
drc.add_enclosure("nwell",
|
||||
layer="active",
|
||||
enclosure=0.18,
|
||||
extension=0.18)
|
||||
|
||||
# nsd/psd.5a
|
||||
drc.add_enclosure("implant",
|
||||
layer="active",
|
||||
enclosure=0.125)
|
||||
|
||||
# Same as active enclosure?
|
||||
drc["implant_to_contact"] = 0.070
|
||||
# nsd/psd.1 nsd/psd.2
|
||||
drc.add_layer("implant",
|
||||
width=0.380,
|
||||
spacing=0.380,
|
||||
area=0.265)
|
||||
|
||||
# licon.1, licon.2
|
||||
drc.add_layer("contact",
|
||||
width=0.170,
|
||||
spacing=0.170)
|
||||
# licon.5c (0.06 extension), (licon.7 for extension)
|
||||
drc.add_enclosure("active",
|
||||
layer="contact",
|
||||
enclosure=0.040,
|
||||
extension=0.060)
|
||||
# licon.7
|
||||
drc["tap_extend_contact"] = 0.120
|
||||
|
||||
# licon.8 Minimum enclosure of poly around contact
|
||||
drc.add_enclosure("poly",
|
||||
layer="contact",
|
||||
enclosure=0.08,
|
||||
extension=0.08)
|
||||
# licon.11a
|
||||
drc["active_contact_to_gate"] = 0.050
|
||||
# npc.4 > licon.14 0.19 > licon.11a
|
||||
drc["poly_contact_to_gate"] = 0.270
|
||||
# licon.15
|
||||
drc["npc_enclose_poly"] = 0.1
|
||||
|
||||
# li.1, li.3
|
||||
drc.add_layer("li",
|
||||
width=0.170,
|
||||
spacing=0.170)
|
||||
|
||||
# licon.5
|
||||
drc.add_enclosure("li",
|
||||
layer="contact",
|
||||
enclosure=0,
|
||||
extension=0.080)
|
||||
|
||||
drc.add_enclosure("li",
|
||||
layer="mcon",
|
||||
enclosure=0,
|
||||
extension=0.080)
|
||||
# mcon.1, mcon.2
|
||||
drc.add_layer("mcon",
|
||||
width=0.170,
|
||||
spacing=0.210)
|
||||
|
||||
# m1.1 Minimum width of metal1
|
||||
# m1.2 Minimum spacing of metal1
|
||||
# m1.6 Minimum area of metal1
|
||||
drc.add_layer("m1",
|
||||
width=0.140,
|
||||
spacing=0.140,
|
||||
area=0.083)
|
||||
# m1.4 Minimum enclosure of metal1
|
||||
# m1.5 Minimum enclosure around contact on two opposite sides
|
||||
drc.add_enclosure("m1",
|
||||
layer="mcon",
|
||||
enclosure=0.030,
|
||||
extension=0.060)
|
||||
# via.4a Minimum enclosure around via1
|
||||
# via.5a Minimum enclosure around via1 on two opposite sides
|
||||
drc.add_enclosure("m1",
|
||||
layer="via1",
|
||||
enclosure=0.055,
|
||||
extension=0.085)
|
||||
|
||||
# via.1a Minimum width of via1
|
||||
# via.2 Minimum spacing of via1
|
||||
drc.add_layer("via1",
|
||||
width=0.150,
|
||||
spacing=0.170)
|
||||
|
||||
# m2.1 Minimum width of intermediate metal
|
||||
# m2.2 Minimum spacing of intermediate metal
|
||||
# m2.6 Minimum area of metal2
|
||||
drc.add_layer("m2",
|
||||
width=0.140,
|
||||
spacing=0.140,
|
||||
area=0.0676)
|
||||
# m2.4 Minimum enclosure around via1
|
||||
# m2.5 Minimum enclosure around via1 on two opposite sides
|
||||
drc.add_enclosure("m2",
|
||||
layer="via1",
|
||||
enclosure=0.055,
|
||||
extension=0.085)
|
||||
# via2.4 Minimum enclosure around via2
|
||||
# via2.5 Minimum enclosure around via2 on two opposite sides
|
||||
drc.add_enclosure("m2",
|
||||
layer="via2",
|
||||
enclosure=0.040,
|
||||
extension=0.085)
|
||||
|
||||
# via2.1a Minimum width of Via2
|
||||
# via2.2 Minimum spacing of Via2
|
||||
drc.add_layer("via2",
|
||||
width=0.200,
|
||||
spacing=0.200)
|
||||
|
||||
# m3.1 Minimum width of metal3
|
||||
# m3.2 Minimum spacing of metal3
|
||||
# m3.6 Minimum area of metal3
|
||||
drc.add_layer("m3",
|
||||
width=0.300,
|
||||
spacing=0.300,
|
||||
area=0.240)
|
||||
# m3.4 Minimum enclosure around via2
|
||||
drc.add_enclosure("m3",
|
||||
layer="via2",
|
||||
enclosure=0.065)
|
||||
# via3.4 Minimum enclosure around via3
|
||||
# via3.5 Minimum enclosure around via3 on two opposite sides
|
||||
drc.add_enclosure("m3",
|
||||
layer="via3",
|
||||
enclosure=0.060,
|
||||
extension=0.090)
|
||||
|
||||
# via3.1 Minimum width of Via3
|
||||
# via3.2 Minimum spacing of Via3
|
||||
drc.add_layer("via3",
|
||||
width=0.200,
|
||||
spacing=0.200)
|
||||
|
||||
# m4.1 Minimum width of metal4
|
||||
# m4.2 Minimum spacing of metal4
|
||||
# m4.7 Minimum area of metal4
|
||||
drc.add_layer("m4",
|
||||
width=0.300,
|
||||
spacing=0.300,
|
||||
area=0.240)
|
||||
# m4.3 Minimum enclosure around via3
|
||||
drc.add_enclosure("m4",
|
||||
layer="via3",
|
||||
enclosure=0.065)
|
||||
# FIXME: Wrong rule m4.3 Minimum enclosure around via3
|
||||
drc.add_enclosure("m4",
|
||||
layer="via4",
|
||||
enclosure=0.060)
|
||||
|
||||
|
||||
# via4.1 Minimum width of Via4
|
||||
# via4.2 Minimum spacing of Via4
|
||||
drc.add_layer("via4",
|
||||
width=0.800,
|
||||
spacing=0.800)
|
||||
|
||||
# FIXME: Wrong rules
|
||||
# m5.1 Minimum width of metal5
|
||||
# m5.2 Minimum spacing of metal5
|
||||
# m5.7 Minimum area of metal5
|
||||
drc.add_layer("m5",
|
||||
width=1.600,
|
||||
spacing=1.600,
|
||||
area=4.000)
|
||||
# m5.3 Minimum enclosure around via4
|
||||
drc.add_enclosure("m5",
|
||||
layer="via4",
|
||||
enclosure=0.310)
|
||||
|
||||
|
||||
|
||||
# Metal 5-10 are ommitted
|
||||
|
||||
###################################################
|
||||
# Spice Simulation Parameters
|
||||
###################################################
|
||||
|
||||
# spice info
|
||||
spice = {}
|
||||
spice["nmos"] = "sky130_fd_pr__nfet_01v8"
|
||||
spice["pmos"] = "sky130_fd_pr__pfet_01v8"
|
||||
spice["power"]="vccd1"
|
||||
spice["ground"]="vssd1"
|
||||
|
||||
# whether or not the device model is actually a subckt
|
||||
spice["device_prefix"] = "X"
|
||||
|
||||
spice["fet_libraries"] = { "TT": [[os.environ.get("SPICE_MODEL_DIR") + "/sky130.lib.spice", "tt"]],
|
||||
"SS": [[os.environ.get("SPICE_MODEL_DIR") + "/sky130.lib.spice", "ss"]],
|
||||
"FF": [[os.environ.get("SPICE_MODEL_DIR") + "/sky130.lib.spice", "ff"]],
|
||||
"SF": [[os.environ.get("SPICE_MODEL_DIR") + "/sky130.lib.spice", "sf"]],
|
||||
"FS": [[os.environ.get("SPICE_MODEL_DIR") + "/sky130.lib.spice", "fs"]] }
|
||||
|
||||
# spice stimulus related variables
|
||||
spice["feasible_period"] = 10 # estimated feasible period in ns
|
||||
spice["supply_voltages"] = [1.7, 1.8, 1.9] # Supply voltage corners in [Volts]
|
||||
spice["nom_supply_voltage"] = 1.8 # Nominal supply voltage in [Volts]
|
||||
spice["rise_time"] = 0.005 # rise time in [Nano-seconds]
|
||||
spice["fall_time"] = 0.005 # fall time in [Nano-seconds]
|
||||
spice["temperatures"] = [0, 25, 100] # Temperature corners (celcius)
|
||||
spice["nom_temperature"] = 25 # Nominal temperature (celcius)
|
||||
|
||||
# analytical delay parameters
|
||||
spice["nom_threshold"] = 0.49 # Typical Threshold voltage in Volts
|
||||
spice["wire_unit_r"] = 0.125 # Unit wire resistance in ohms/square
|
||||
spice["wire_unit_c"] = 0.134 # Unit wire capacitance ff/um^2
|
||||
spice["min_tx_drain_c"] = 0.7 # Minimum transistor drain capacitance in ff
|
||||
spice["min_tx_gate_c"] = 0.2 # Minimum transistor gate capacitance in ff
|
||||
spice["dff_setup"] = 102.5391 # DFF setup time in ps
|
||||
spice["dff_hold"] = -56 # DFF hold time in ps
|
||||
spice["dff_in_cap"] = 6.89 # Input capacitance (D) [Femto-farad]
|
||||
spice["dff_out_cap"] = 6.89 # Output capacitance (Q) [Femto-farad]
|
||||
|
||||
# analytical power parameters, many values are temporary
|
||||
spice["bitcell_leakage"] = 1 # Leakage power of a single bitcell in nW
|
||||
spice["inv_leakage"] = 1 # Leakage power of inverter in nW
|
||||
spice["nand2_leakage"] = 1 # Leakage power of 2-input nand in nW
|
||||
spice["nand3_leakage"] = 1 # Leakage power of 3-input nand in nW
|
||||
spice["nand4_leakage"] = 1 # Leakage power of 4-input nand in nW
|
||||
spice["nor2_leakage"] = 1 # Leakage power of 2-input nor in nW
|
||||
spice["dff_leakage"] = 1 # Leakage power of flop in nW
|
||||
|
||||
spice["default_event_frequency"] = 100 # Default event activity of every gate. MHz
|
||||
|
||||
# Parameters related to sense amp enable timing and delay chain/RBL sizing
|
||||
parameter["le_tau"] = 2.25 # In pico-seconds.
|
||||
parameter["cap_relative_per_ff"] = 7.5 # Units of Relative Capacitance/ Femto-Farad
|
||||
parameter["dff_clk_cin"] = 30.6 # relative capacitance
|
||||
parameter["6tcell_wl_cin"] = 3 # relative capacitance
|
||||
parameter["min_inv_para_delay"] = 2.4 # Tau delay units
|
||||
parameter["sa_en_pmos_size"] = 0.72 # micro-meters
|
||||
parameter["sa_en_nmos_size"] = 0.27 # micro-meters
|
||||
parameter["sa_inv_pmos_size"] = 0.54 # micro-meters
|
||||
parameter["sa_inv_nmos_size"] = 0.27 # micro-meters
|
||||
parameter["bitcell_drain_cap"] = 0.1 # In Femto-Farad, approximation of drain capacitance
|
||||
|
||||
###################################################
|
||||
# Technology Tool Preferences
|
||||
###################################################
|
||||
|
||||
if use_calibre:
|
||||
drc_name = "calibre"
|
||||
lvs_name = "calibre"
|
||||
pex_name = "calibre"
|
||||
elif use_klayout:
|
||||
drc_name = "klayout"
|
||||
lvs_name = "klayout"
|
||||
pex_name = "klayout"
|
||||
else:
|
||||
drc_name = "magic"
|
||||
lvs_name = "netgen"
|
||||
pex_name = "magic"
|
||||
|
||||
|
||||
# This is used by uniqify to not rename the library cells
|
||||
library_prefix_name = "sky130_fd_bd_sram__"
|
||||
# List of cells to skip running DRC/LVS on directly
|
||||
# This will look for a maglef file and copy it over the mag file
|
||||
# before DRC after extraction
|
||||
|
||||
# gds flatglob sky130_fd_bd_sram__openram_sp_cell_opt1a_cell
|
||||
# gds flatglob sky130_fd_bd_sram__openram_sp_cell_opt1a_replica_ce
|
||||
# gds flatglob sky130_fd_bd_sram__openram_sp_cell_opt1_replica_cell
|
||||
# gds flatglob sky130_fd_bd_sram__openram_sp_cell_opt1_replica_ce
|
||||
# gds flatglob sky130_fd_bd_sram__openram_sp_cell_opt1_replica_cell
|
||||
# gds flatglob sky130_fd_bd_sram__openram_sp_cell_opt1a_cell
|
||||
# gds flatglob sky130_fd_bd_sram__sram_sp_cell_fom_serifs
|
||||
|
||||
flatglob = ["*_?mos_m*",
|
||||
"sky130_fd_bd_sram__sram_sp_cell_fom_serifs",
|
||||
|
||||
"sky130_fd_bd_sram__sram_sp_cell",
|
||||
"sky130_fd_bd_sram__openram_sp_cell_opt1_replica_cell",
|
||||
"sky130_fd_bd_sram__openram_sp_cell_opt1a_replica_cell",
|
||||
|
||||
"sky130_fd_bd_sram__sram_sp_cell_opt1_ce",
|
||||
"sky130_fd_bd_sram__openram_sp_cell_opt1_replica_ce",
|
||||
"sky130_fd_bd_sram__openram_sp_cell_opt1a_replica_ce",
|
||||
"sky130_fd_bd_sram__sram_sp_wlstrap_ce",
|
||||
"sky130_fd_bd_sram__sram_sp_wlstrap_p_ce"]
|
||||
|
||||
blackbox_cells = ["sky130_fd_bd_sram__openram_dp_cell",
|
||||
"sky130_fd_bd_sram__openram_dp_cell_dummy",
|
||||
"sky130_fd_bd_sram__openram_dp_cell_replica",
|
||||
|
||||
"sky130_fd_bd_sram__openram_sp_cell_opt1_noblcon",
|
||||
"sky130_fd_bd_sram__openram_sp_cell_opt1a_noblcon",
|
||||
"sky130_fd_bd_sram__openram_sp_colend_replica",
|
||||
"sky130_fd_bd_sram__openram_sp_colenda_replica",
|
||||
"sky130_fd_bd_sram__sram_sp_cell_opt1a",
|
||||
"sky130_fd_bd_sram__openram_sp_cell_opt1a_dummy",
|
||||
"sky130_fd_bd_sram__openram_sp_cell_opt1_dummy",
|
||||
"sky130_fd_bd_sram__sram_sp_cell_opt1_ce",
|
||||
"sky130_fd_bd_sram__sram_sp_cell_opt1",
|
||||
"sky130_fd_bd_sram__openram_sp_cell_opt1_replica",
|
||||
"sky130_fd_bd_sram__openram_sp_cell_opt1a_replica",
|
||||
"sky130_fd_bd_sram__sram_sp_colend",
|
||||
"sky130_fd_bd_sram__sram_sp_colend_cent",
|
||||
"sky130_fd_bd_sram__sram_sp_colend_p_cent",
|
||||
"sky130_fd_bd_sram__sram_sp_colenda",
|
||||
"sky130_fd_bd_sram__sram_sp_colenda_cent",
|
||||
"sky130_fd_bd_sram__sram_sp_colenda_p_cent",
|
||||
"sky130_fd_bd_sram__sram_sp_rowend",
|
||||
"sky130_fd_bd_sram__sram_sp_rowenda",
|
||||
"sky130_fd_bd_sram__openram_sp_rowend_replica",
|
||||
"sky130_fd_bd_sram__openram_sp_rowenda_replica",
|
||||
"sky130_fd_bd_sram__sram_sp_corner",
|
||||
"sky130_fd_bd_sram__sram_sp_cornera",
|
||||
"sky130_fd_bd_sram__sram_sp_cornerb",
|
||||
"sky130_fd_bd_sram__sram_sp_wlstrapa",
|
||||
"sky130_fd_bd_sram__sram_sp_wlstrap_ce",
|
||||
"sky130_fd_bd_sram__sram_sp_wlstrap",
|
||||
"sky130_fd_bd_sram__sram_sp_wlstrap_p_ce",
|
||||
"sky130_fd_bd_sram__sram_sp_wlstrap_p",
|
||||
"sky130_fd_bd_sram__sram_sp_wlstrapa_p"]
|
||||
Reference in New Issue
Block a user