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Add missing contact to vdd pins.

This commit is contained in:
mrg 2020-06-30 13:26:38 -07:00
parent 5626fd182e
commit a48ea52253
2 changed files with 43 additions and 48 deletions
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15
compiler/modules/dff_array.py
View File

@ -7,12 +7,11 @@
# #
import debug import debug
import design import design
from tech import drc
from math import log
from vector import vector from vector import vector
from sram_factory import factory from sram_factory import factory
from globals import OPTS from globals import OPTS
class dff_array(design.design): class dff_array(design.design):
""" """
This is a simple row (or multiple rows) of flops. This is a simple row (or multiple rows) of flops.
@ -79,7 +78,6 @@ class dff_array(design.design):
def place_dff_array(self): def place_dff_array(self):
for row in range(self.rows): for row in range(self.rows):
for col in range(self.columns): for col in range(self.columns):
name = "dff_r{0}_c{1}".format(row,col)
if (row % 2 == 0): if (row % 2 == 0):
base = vector(col * self.dff.width, row * self.dff.height) base = vector(col * self.dff.width, row * self.dff.height)
mirror = "R0" mirror = "R0"
@ -109,18 +107,16 @@ class dff_array(design.design):
return dout_name return dout_name
def add_layout_pins(self): def add_layout_pins(self):
for row in range(self.rows): for row in range(self.rows):
for col in range(self.columns): for col in range(self.columns):
# Continous vdd rail along with label. # Continous vdd rail along with label.
vdd_pin=self.dff_insts[row, col].get_pin("vdd") vdd_pin=self.dff_insts[row, col].get_pin("vdd")
self.add_power_pin("vdd", vdd_pin.center()) self.add_power_pin("vdd", vdd_pin.center(), start_layer=vdd_pin.layer)
# Continous gnd rail along with label. # Continous gnd rail along with label.
gnd_pin=self.dff_insts[row, col].get_pin("gnd") gnd_pin=self.dff_insts[row, col].get_pin("gnd")
self.add_power_pin("gnd", gnd_pin.center()) self.add_power_pin("gnd", gnd_pin.center(), start_layer=gnd_pin.layer)
for row in range(self.rows): for row in range(self.rows):
for col in range(self.columns): for col in range(self.columns):
@ -140,8 +136,6 @@ class dff_array(design.design):
width=dout_pin.width(), width=dout_pin.width(),
height=dout_pin.height()) height=dout_pin.height())
# Create vertical spines to a single horizontal rail # Create vertical spines to a single horizontal rail
clk_pin = self.dff_insts[0, 0].get_pin(self.dff.clk_pin) clk_pin = self.dff_insts[0, 0].get_pin(self.dff.clk_pin)
clk_ypos = 2 * self.m3_pitch + self.m3_width clk_ypos = 2 * self.m3_pitch + self.m3_width
@ -158,7 +152,8 @@ class dff_array(design.design):
width=self.m2_width, width=self.m2_width,
height=self.height) height=self.height)
# Drop a via to the M3 pin # Drop a via to the M3 pin
self.add_via_center(layers=self.m2_stack, self.add_via_stack_center(from_layer=clk_pin.layer,
to_layer="m3",
offset=vector(clk_pin.cx(), clk_ypos)) offset=vector(clk_pin.cx(), clk_ypos))
def get_clk_cin(self): def get_clk_cin(self):

4
compiler/modules/dff_buf_array.py
View File

@ -167,11 +167,11 @@ class dff_buf_array(design.design):
for col in range(self.columns): for col in range(self.columns):
# Continous vdd rail along with label. # Continous vdd rail along with label.
vdd_pin=self.dff_insts[row, col].get_pin("vdd") vdd_pin=self.dff_insts[row, col].get_pin("vdd")
self.add_power_pin("vdd", vdd_pin.lc()) self.add_power_pin("vdd", vdd_pin.lc(), start_layer=vdd_pin.layer)
# Continous gnd rail along with label. # Continous gnd rail along with label.
gnd_pin=self.dff_insts[row, col].get_pin("gnd") gnd_pin=self.dff_insts[row, col].get_pin("gnd")
self.add_power_pin("gnd", gnd_pin.lc()) self.add_power_pin("gnd", gnd_pin.lc(), start_layer=gnd_pin.layer)
def add_layout_pins(self): def add_layout_pins(self):