Merge pull request #58 from bkoppelmann/dev

Custom Module API

compiler/globals.py

@@ -504,6 +504,11 @@ def import_tech():
     except ImportError:
         debug.error("Could not load tech module.", -1)
 
+    # Add custom modules of the technology to the path, if they exist
+    custom_mod_path = os.path.join(tech_path, "modules/")
+    if os.path.exists(custom_mod_path):
+        sys.path.append(custom_mod_path)
+
 
 def print_time(name, now_time, last_time=None, indentation=2):
     """ Print a statement about the time delta. """

compiler/modules/module_type.py

@@ -0,0 +1,70 @@
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2019 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+
+class ModuleType():
+    """
+    This is a class that maps cell names to python classes implementing them.
+    """
+    def __init__(self):
+        self.names = {}
+        self.names['contact']                       = 'contact'
+        self.names['precharge']                     = 'precharge'
+        self.names['pinv']                          = 'pinv'
+        self.names['dff_buf']                       = 'dff_buf'
+        self.names['sense_amp']                     = 'sense_amp'
+        self.names['bitcell']                       = 'bitcell'
+        self.names['port_data']                     = 'port_data'
+        self.names['port_address']                  = 'port_address'
+        self.names['replica_bitcell_array']         = 'replica_bitcell_array'
+        self.names['bank_select']                   = 'bank_select'
+        self.names['dff']                           = 'dff'
+        self.names['pinvbuf']                       = 'pinvbuf'
+        self.names['hierarchical_predecode2x4']     = 'hierarchical_predecode2x4'
+        self.names['hierarchical_predecode3x8']     = 'hierarchical_predecode3x8'
+        self.names['replica_bitcell']               = 'replica_bitcell'
+        self.names['dummy_bitcell']                 = 'dummy_bitcell'
+        self.names['bitcell']                       = 'bitcell'
+        self.names['pnor2']                         = 'pnor2'
+        self.names['pnand2']                        = 'pnand2'
+        self.names['precharge_array']               = 'precharge_array'
+        self.names['sense_amp_array']               = 'sense_amp_array'
+        self.names['column_mux_array']              = 'column_mux_array'
+        self.names['write_driver_array']            = 'write_driver_array'
+        self.names['write_mask_and_array']          = 'write_mask_and_array'
+        self.names['pand2']                         = 'pand2'
+        self.names['write_driver']                  = 'write_driver'
+        self.names['dff_buf_array']                 = 'dff_buf_array'
+        self.names['pdriver']                       = 'pdriver'
+        self.names['pand3']                         = 'pand3'
+        self.names['delay_chain']                   = 'delay_chain'
+        self.names['decoder']                       = 'decoder'
+        self.names['wordline_driver']               = 'wordline_driver'
+        self.names['tri_gate']                      = 'tri_gate'
+        self.names['tri_gate_array']                = 'tri_gate_array'
+        self.names['bitcell_array']                 = 'bitcell_array'
+        self.names['replica_column']                = 'replica_column'
+        self.names['dummy_array']                   = 'dummy_array'
+        self.names['single_level_column_mux_array'] = 'single_level_column_mux_array'
+        self.names['single_level_column_mux']       = 'single_level_column_mux'
+        self.names['sram']                          = 'sram'
+        self.names['ptx']                           = 'ptx'
+        self.names['hierarchical_decoder']          = 'hierarchical_decoder'
+        self.names['pbuf']                          = 'pbuf'
+        self.names['control_logic']                 = 'control_logic'
+        self.names['bank']                          = 'bank'
+        self.names['pbitcell']                      = 'pbitcell'
+        self.names['pnand3']                        = 'pnand3'
+        self.names['pwrite_driver']                 = 'pwrite_driver'
+        self.names['ptristate_inv']                 = 'ptristate_inv'
+        self.names['ptristate_buf']                 = 'ptristate_buf'
+
+    def __setitem__(self, b, c):
+        self.names[b] = c
+
+    def __getitem__(self, b):
+        return self.names[b]

compiler/sram_factory.py

@@ -6,6 +6,7 @@
 # All rights reserved.
 #
 from globals import OPTS
+from tech import tech_modules
 
 
 class sram_factory:
@@ -37,6 +38,8 @@ class sram_factory:
         A generic function to create a module with a given module_type.
         The args are passed directly to the module constructor.
         """
+
+        module_type = tech_modules[module_type]
         # if name!="":
         #     # This is a special case where the name and type don't match
         #     # Can't be overridden in the config file

technology/freepdk45/tech/tech.py

@@ -7,10 +7,17 @@
 #
 import os
 from design_rules import *
+from module_type import *
 
 """
 File containing the process technology parameters for FreePDK 45nm.
 """
+# This uses the default classes to instantiate module from
+# '$OPENRAM_HOME/compiler/modules'.
+# Using tech_modules['cellname'] you can override each class by providing a custom
+# implementation in '$OPENRAM_TECHDIR/modules/'
+# For example: tech_modules['contact'] = 'contact_freepdk45'
+tech_modules = ModuleType()
 
 #GDS file info
 GDS = {}

technology/scn3me_subm/tech/tech.py

@@ -1,9 +1,16 @@
 import os
 from design_rules import *
+from module_type import *
 
 """
 File containing the process technology parameters for SCMOS 3me, subm, 180nm.
 """
+# This uses the default classes to instantiate module from
+# '$OPENRAM_HOME/compiler/modules'.
+# Using tech_modules['cellname'] you can override each class by providing a custom
+# implementation in '$OPENRAM_TECHDIR/modules/'
+# For example: tech_modules['contact'] = 'contact_scn3me'
+tech_modules = ModuleType()
 
 #GDS file info
 GDS={}

technology/scn4m_subm/tech/tech.py

@@ -7,10 +7,17 @@
 #
 import os
 from design_rules import *
+from module_type import *
 
 """
 File containing the process technology parameters for SCMOS 4m, 0.35um
 """
+# This uses the default classes to instantiate module from
+# '$OPENRAM_HOME/compiler/modules'.
+# Using tech_modules['cellname'] you can override each class by providing a custom
+# implementation in '$OPENRAM_TECHDIR/modules/'
+# For example: tech_modules['contact'] = 'contact_scn4m'
+tech_modules = ModuleType()
 
 #GDS file info
 GDS={}