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Fixed module from writing syntax issues

This commit is contained in:
Gary Mejia 2023-06-13 17:30:38 -07:00
parent 692acd2066
commit a3284e8b47
1 changed files with 8 additions and 9 deletions
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15
compiler/base/rom_verilog.py
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@ -80,17 +80,14 @@ class rom_verilog:
self.vf.write(" reg [DATA_WIDTH-1:0] mem [0:ROM_DEPTH-1];\n\n") self.vf.write(" reg [DATA_WIDTH-1:0] mem [0:ROM_DEPTH-1];\n\n")
#write memory init here #write memory init here
self.vf.write(" inital begin\n") self.vf.write(f" initial begin\n")
if self.data_type == "bin": if self.data_type == "bin":
self.vf.write(f" //binary data\n") self.vf.write(f" $readmemb(\"{self.rom_data}\",mem,0,ROM_DEPTH-1);\n")
self.vf.write(f" $memreadb(\"{self.rom_data}\",mem)\n")
elif self.data_type == "hex": elif self.data_type == "hex":
self.vf.write(f" //hex data\n") self.vf.write(f" $readmemh(\"{self.rom_data}\",mem,0, ROM_DEPTH-1);\n")
self.vf.write(f" $memreadh(\"{self.rom_data}\",mem)\n")
else: else:
raise ValueError(f"Data type {self.data_type} is not supported!") raise ValueError(f"Data type: {self.data_type} is not supported!")
self.vf.write(f" end\n\n")
self.vf.write(" end\n\n")
for port in self.all_ports: for port in self.all_ports:
self.register_inputs(port) self.register_inputs(port)
@ -115,9 +112,11 @@ class rom_verilog:
Create the input regs for the given port. Create the input regs for the given port.
""" """
self.vf.write(" reg csb{0}_reg;\n".format(port)) self.vf.write(" reg csb{0}_reg;\n".format(port))
self.vf.write(" reg [ADDR_WIDTH-1:0] addr{0}_reg;\n".format(port))
if port in self.read_ports: if port in self.read_ports:
self.vf.write(" reg [DATA_WIDTH-1:0] dout{0};\n".format(port)) self.vf.write(" reg [DATA_WIDTH-1:0] dout{0};\n".format(port))
def add_flops(self, port): def add_flops(self, port):
""" """
Add the flop behavior logic for a port. Add the flop behavior logic for a port.