mirror of https://github.com/VLSIDA/OpenRAM.git
Fix missing nand4_leakage #97
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@ -438,6 +438,7 @@ spice["bitcell_leakage"] = 1 # Leakage power of a single bitcell in nW
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spice["inv_leakage"] = 1 # Leakage power of inverter in nW
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spice["nand2_leakage"] = 1 # Leakage power of 2-input nand in nW
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spice["nand3_leakage"] = 1 # Leakage power of 3-input nand in nW
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spice["nand4_leakage"] = 1 # Leakage power of 4-input nand in nW
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spice["nor2_leakage"] = 1 # Leakage power of 2-input nor in nW
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spice["dff_leakage"] = 1 # Leakage power of flop in nW
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@ -385,6 +385,7 @@ spice["bitcell_leakage"] = 1 # Leakage power of a single bitcell in nW
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spice["inv_leakage"] = 1 # Leakage power of inverter in nW
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spice["nand2_leakage"] = 1 # Leakage power of 2-input nand in nW
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spice["nand3_leakage"] = 1 # Leakage power of 3-input nand in nW
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spice["nand4_leakage"] = 1 # Leakage power of 4-input nand in nW
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spice["nor2_leakage"] = 1 # Leakage power of 2-input nor in nW
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spice["dff_leakage"] = 1 # Leakage power of flop in nW
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