Split DATA into DIN and DOUT in characterizer

compiler/characterizer/delay.py

@@ -78,11 +78,7 @@ class delay():
 
         self.sf.write("\n* SRAM output loads\n")
         for i in range(self.word_size):
-            self.sf.write("CD{0} d[{0}] 0 {1}f\n".format(i,self.load))
+            self.sf.write("CD{0} DOUT[{0}] 0 {1}f\n".format(i,self.load))
-        
-        # add access transistors for data-bus
-        self.sf.write("\n* Transmission Gates for data-bus and control signals\n")
-        self.stim.inst_accesstx(dbits=self.word_size)
         
 
     def write_delay_stimulus(self):
@@ -112,11 +108,11 @@ class delay():
         for i in range(self.word_size):
             if i == self.probe_data:
                 self.gen_data(clk_times=self.cycle_times,
-                              sig_name="data[{0}]".format(i))
+                              sig_name="DIN[{0}]".format(i))
 
 
             else:
-                self.stim.gen_constant(sig_name="d[{0}]".format(i),
+                self.stim.gen_constant(sig_name="DIN[{0}]".format(i),
                                        v_val=0)
 
         self.gen_addr(clk_times=self.cycle_times,
@@ -172,7 +168,7 @@ class delay():
         # generate data and addr signals
         self.sf.write("\n* Generation of data and address signals\n")
         for i in range(self.word_size):
-            self.stim.gen_constant(sig_name="d[{0}]".format(i),
+            self.stim.gen_constant(sig_name="DIN[{0}]".format(i),
                                    v_val=0)
         for i in range(self.addr_size):
             self.stim.gen_constant(sig_name="A[{0}]".format(i),
@@ -208,7 +204,7 @@ class delay():
 
         # Trigger on the clk of the appropriate cycle
         trig_name = "clk"
-        targ_name = "{0}".format("d[{0}]".format(self.probe_data))
+        targ_name = "{0}".format("DIN[{0}]".format(self.probe_data))
         trig_val = targ_val = 0.5 * self.vdd_voltage
 
         # Delay the target to measure after the negative edge
@@ -783,12 +779,6 @@ class delay():
         values = [1, 0, 0, 0, 1, 1, 0, 0, 1, 1]
         self.stim.gen_pwl("web", clk_times, values, self.period, self.slew, 0.05)
 
-        # Keep acc_en deasserted in NOP for measuring >1 period
-        values = [1, 0, 0, 0, 1, 1, 0, 0, 1, 1]
-        self.stim.gen_pwl("acc_en", clk_times, values, self.period, self.slew, 0)
-        values = [0, 1, 1, 1, 0, 0, 1, 1, 0, 0]
-        self.stim.gen_pwl("acc_en_inv", clk_times, values, self.period, self.slew, 0)
-        
     def gen_oeb(self, clk_times):
         """ Generates the PWL WEb signal """
         # values for NOP, W1, W0, W1, R0, W1, W0, R1, NOP

compiler/characterizer/lib.py

@@ -440,9 +440,7 @@ class lib:
 
     def compute_delay(self):
         """ Do the analysis if we haven't characterized the SRAM yet """
-        try:
+        if not hasattr(self,"d"):
-            self.d
-        except AttributeError:
             self.d = delay(self.sram, self.sp_file, self.corner)
             if self.use_model:
                 self.char_results = self.d.analytical_delay(self.sram,self.slews,self.loads)
@@ -455,9 +453,7 @@ class lib:
     def compute_setup_hold(self):
         """ Do the analysis if we haven't characterized a FF yet """
         # Do the analysis if we haven't characterized a FF yet
-        try:
+        if not hasattr(self,"sh"):
-            self.sh
-        except AttributeError:
             self.sh = setup_hold(self.corner)
             if self.use_model:
                 self.times = self.sh.analytical_setuphold(self.slews,self.loads)

compiler/characterizer/stimuli.py

@@ -34,12 +34,14 @@ class stimuli():
         """ Function to instatiate an SRAM subckt. """
         self.sf.write("Xsram ")
         for i in range(dbits):
-            self.sf.write("D[{0}] ".format(i))
+            self.sf.write("DIN[{0}] ".format(i))
         for i in range(abits):
             self.sf.write("A[{0}] ".format(i))
         for i in tech.spice["control_signals"]:
             self.sf.write("{0} ".format(i))
         self.sf.write("{0} ".format(tech.spice["clk"]))
+        for i in range(dbits):
+            self.sf.write("DOUT[{0}] ".format(i))
         self.sf.write("{0} {1} ".format(self.vdd_name, self.gnd_name))
         self.sf.write("{0}\n".format(sram_name))
 
@@ -110,23 +112,6 @@ class stimuli():
                                                                            "test"+self.vdd_name,
                                                                            "test"+self.gnd_name))
 
-        
-    def inst_accesstx(self, dbits):
-        """ Adds transmission gate for inputs to data-bus (only for sim purposes) """
-        self.sf.write("* Tx Pin-list: Drain Gate Source Body\n")
-        for i in range(dbits):
-            pmos_access_string="mp{0} DATA[{0}] acc_en D[{0}] {1} {2} w={3}u l={4}u\n"
-            self.sf.write(pmos_access_string.format(i,
-                                                    "test"+self.vdd_name,
-                                                    self.pmos_name,
-                                                    2 * self.tx_width,
-                                                    self.tx_length))
-            nmos_access_string="mn{0} DATA[{0}] acc_en_inv D[{0}] {1} {2} w={3}u l={4}u\n"
-            self.sf.write(nmos_access_string.format(i,
-                                                    "test"+self.gnd_name,
-                                                    self.nmos_name,
-                                                    2 * self.tx_width,
-                                                    self.tx_length))
 
     def gen_pulse(self, sig_name, v1, v2, offset, period, t_rise, t_fall):
         """