Replaced instances of addr_size with bank_addr

compiler/base/verilog.py

@@ -79,7 +79,7 @@ class verilog:
             self.num_wmasks = int(math.ceil(self.word_size / self.write_size))
             self.vf.write("  parameter NUM_WMASKS = {0} ;\n".format(self.num_wmasks))
         self.vf.write("  parameter DATA_WIDTH = {0} ;\n".format(self.word_size + self.num_spare_cols))
-        self.vf.write("  parameter ADDR_WIDTH = {0} ;\n".format(self.addr_size))
+        self.vf.write("  parameter ADDR_WIDTH = {0} ;\n".format(self.bank_addr_size))
         self.vf.write("  parameter RAM_DEPTH = 1 << ADDR_WIDTH;\n")
         self.vf.write("  // FIXME: This delay is arbitrary.\n")
         self.vf.write("  parameter DELAY = 3 ;\n")

compiler/base/verilog_template.v

@@ -1,191 +0,0 @@
-// OpenRAM SRAM model
-// Words: #$WORDS$#
-// Word size: #$WORD_SIZE$#
-#<WRITE_SIZE_CMT
-// Write size: #$WRITE_SIZE$#
-#>WRITE_SIZE_CMT
-
-module #$MODULE_NAME$# (
-#<PORTS
-`ifdef USE_POWER_PINS
-    #$VDD$#,
-    #$GND$#,
-`endif
-#<WRITE_MASK
-    wmask#$PORT_NUM$#,
-#>WRITE_MASK
-#<SPARE_WEN
-    spare_wen#$PORT_NUM$#,
-#<SPARE_WEN
-#<RW_PORT
-// Port #$PORT_NUM$#: RW
-    clk#$PORT_NUM#$,csb#$PORT_NUM$#,web$#PORT_NUM$#,addr#$PORT_NUM$#,din#$PORT_NUM$#,dout#$PORT_NUM$#
-#>RW_PORT
-#<R_PORT
-// Port #$PORT_NUM$#: R
-    clk#$PORT_NUM#$,csb#$PORT_NUM$#,addr#PORT_NUM$#,dout#PORT_NUM$#
-#>RW_PORT
-#<W_PORT
-// Port #$PORT_NUM$#: W
-    clk#$PORT_NUM#$,csb#$PORT_NUM$#,web$#PORT_NUM$#,addr#PORT_NUM$#,din#PORT_NUM$#
-#>W_PORT
-#>PORTS
-  );
-#<WMASK_PAR
-  parameter NUM_WMASK = #$NUM_WMASK#$ ;
-#>WMASK_PAR
-  parameter DATA_WIDTH = #$DATA_WIDTH$# ;
-  parameter ADDR_WIDTH = #$ADD_WIDTH$# ;
-  parameter RAM_DEPTH = 1 << ADDR_WIDTH;
-  // FIXME: This delay is arbitrary.
-  parameter DELAY = 3 ;
-  parameter VERBOSE = 1 ; //Set to 0 to only display warnings
-  parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary
-
-`ifdef USE_POWER_PINS
-    inout #$VDD$#;
-    inout #$GND$#;
-`endif
-
-#<WRITE_MASK
-    input [NUM_WMASK-1:0] wmask#$PORT_NUM$#;
-#>WRITE_MASK
-#<SPARE_WEN_SINGLE
-    input spare_wen#$PORT_NUM$#;
-#<SPARE_WEN_SINGLE
-#<SPARE_WEN_MULT
-    input [#$NUM_SPARE_COL$#-1:0] spare_wen;
-#<SPARE_WEN_MULT
-#<RW_PORT
-    input clk#$PORT_NUM#$;
-    input csb#$PORT_NUM$#;
-    input web#$PORT_NUM$#;
-    input [ADDR_WIDTH-1:0] addr#$PORT_NUM$#;
-    input [DATA_WIDTH-1:0] din#$PORT_NUM$#;
-    output [DATA_WIDTH-1:0] dout#$PORT_NUM$#;
-#>RW_PORT
-#<R_PORT
-    input clk#$PORT_NUM#$;
-    input csb#$PORT_NUM$#;
-    input [ADDR_WIDTH-1:0] addr#$PORT_NUM$#;
-    output [DATA_WIDTH-1:0] dout#$PORT_NUM$#;
-#>RW_PORT
-#<W_PORT
-// Port 0: RW
-    input clk#$PORT_NUM#$;
-    input csb#$PORT_NUM$#;
-    input web#$PORT_NUM$#;
-    input [ADDR_WIDTH-1:0] addr#$PORT_NUM$#;
-    input [DATA_WIDTH-1:0] din#$PORT_NUM$#;
-    output [DATA_WIDTH-1:0] dout#$PORT_NUM$#;
-    clk#$PORT_NUM#$,csb#$PORT_NUM$#,web$#PORT_NUM$#,addr#PORT_NUM$#,din#PORT_NUM$#,dout#PORT_NUM$#
-#>W_PORT
-
-  reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
-
-#<REGS
-  reg  csb#$PORT_NUM$#_reg;
-  reg  web#$PORT_NUM$#_reg;
-  reg [NUM_WMASK-1:0]  wmask#$PORT_NUM$#_reg;
-  reg spare_wen#$PORT_NUM$#_reg;
-  reg [#$SPARE_COLS$#-1:0]  spare_wen#$PORT_NUM$#_reg;
-  reg [ADDR_WIDTH-1:0]  addr#$PORT_NUM$#_reg;
-  reg [DATA_WIDTH-1:0]  din#$PORT_NUM$#_reg;
-  reg [DATA_WIDTH-1:0]  dout#$PORT_NUM$#;
-#<REGS
-#<FLOPS
-  // All inputs are registers
-  always @(posedge clk#$PORT_NUM$#)
-  begin
-    csb#$PORT_NUM$#_reg = csb#$PORT_NUM$#;
-#<WEB_FLOP
-    web#$PORT_NUM$#_reg = web#$PORT_NUM$#;
-#>WEB_FLOP
-#<W_MASK_FLOP
-    w_mask#$PORT_NUM$#_reg = w_mask#$PORT_NUM$#;
-#>W_MASK_FLOP
-#<SPARE_WEN_FLOP
-    spare_wen#$PORT_NUM$#_reg = spare_wen#$PORT_NUM$#;
-#>SPARE_WEN_FLOP
-    addr#$PORT_NUM$#_reg = addr#$PORT_NUM$#;
-#<RW_CHECKS
-    if (#$WPORT_CONTROL$# && #$RPORT_CONTROL$# && (addr#$WPORT$# == addr#$RPORT$#))
-      $display($time," WARNING: Writing and reading addr#$WPORT$#=%b and addr#$RPORT$#=%b simultaneously!",addr#$WPORT$#,addr#$RPORT$#);
-#>RW_CHECKS
-#<DIN_FLOP
-    din#$PORT_NUM$#_reg = din#$PORT_NUM$#;
-#>DIN_FLOP
-#<DOUT_FLOP
-    #(T_HOLD) dout#$PORT_NUM$# = #$WORD_SIZE$#'bx;
-#>DOUT_FLOP
-#<RW_VERBOSE
-    if ( !csb#$PORT_NUM$#_reg && web#$PORT_NUM$#_reg && VERBOSE )
-      $display($time," Reading %m addr#$PORT_NUM$#=%b dout#$PORT_NUM$#=%b",addr#$PORT_NUM$#_reg,mem[addr#$PORT_NUM$#_reg]);
-    if ( !csb#$PORT_NUM$#_reg && !web#$PORT_NUM$#_reg && VERBOSE )
-#<RW_WMASK
-      $display($time," Writing %m addr#$PORT_NUM$#=%b din#$PORT_NUM$#=%b wmask#$PORT_NUM$#=%b",addr#$PORT_NUM$#_reg,din#$PORT_NUM$#_reg,wmask#$PORT_NUM$#_reg);
-#>RW_WMASK
-#<RW_NO_WMASK
-      $display($time," Writing %m addr#$PORT_NUM$#=%b din#$PORT_NUM$#=%b",addr#$PORT_NUM$#_reg,din#$PORT_NUM$#_reg);
-#>RW_NO_WMASK
-#>RW_VERBOSE
-#<R_VERBOSE
-    if ( !csb#$PORT_NUM$#_reg && VERBOSE )
-      $display($time," Reading %m addr#$PORT_NUM$#=%b dout#$PORT_NUM$#=%b",addr#$PORT_NUM$#_reg,mem[addr#$PORT_NUM$#_reg]);
-#>R_VERBOSE
-#<W_VERBOSE
-if ( !csb#$PORT_NUM$#_reg && VERBOSE )
-#<W_WMASK
-      $display($time," Writing %m addr#$PORT_NUM$#=%b din#$PORT_NUM$#=%b wmask#$PORT_NUM$#=%b",addr#$PORT_NUM$#_reg,din#$PORT_NUM$#_reg,wmask#$PORT_NUM$#_reg);
-#>W_WMASK
-#<W_NO_WMASK
-      $display($time," Writing %m addr#$PORT_NUM$#=%b din#$PORT_NUM$#=%b",addr#$PORT_NUM$#_reg,din#$PORT_NUM$#_reg);
-#>W_NO_WMASK
-#>W_VERBOSE
-  end
-#>FLOPS
-#<W_BLOCK
-  // Memory Write Block Port #$PORT_NUM$#
-  // Write Operation : When web#$PORT_NUM$# = #$PORT_NUM$#, csb#$PORT_NUM$# = #$PORT_NUM$#
-  always @ (negedge clk#$PORT_NUM$#)
-  begin : MEM_WRITE#$PORT_NUM$#
-#<READ
-    if ( !csb#$PORT_NUM$#_reg && !web#$PORT_NUM$#_reg ) begin
-#>READ  
-#<NO_READ
-    if ( !csb#$PORT_NUM$#_reg ) begin
-#>NO_READ
-#<W_MASK
-      if (wmask#$PORT_NUM$#_reg[#$MASK$#])
-              mem[addr#$PORT_NUM$#_reg][#$UPPER$#:#$LOWER$#] = din#$PORT_NUM$#_reg[#$UPPER$#:#$LOWER$#];
-#>W_MASK
-#<NO_W_MASK
-      mem[addr#$PORT_NUM$#_reg][1:#$PORT_NUM$#] = din#$PORT_NUM$#_reg[1:#$PORT_NUM$#];
-#<NO_WMASK
-#<ONE_SPARE_COL
-      if (spare_wen#$PORT_NUM$#_reg)
-        mem[addr#$PORT_NUM$#_reg][#$WORD_SIZE$#] = din#$PORT_NUM$#_reg[#$WORD_SIZE$#];
-#>ONE_SPARE_COL
-#!NUM!0#
-#<SPARE_COLS
-      if (spare_wen#$PORT_NUM$#_reg[#$NUM$#])
-        mem[addr#$PORT_NUM$#_reg][#$NUM$# + #$WORD_SIZE$#] = din#$PORT_NUM$#_reg[#$NUM$#];
-#>SPARE_COLS
-    end
-  end
-#>W_BLOCK
-#<R_BLOCK
-  // Memory Read Block Port #$PORT_NUM$#
-  // Read Operation : When web#$PORT_NUM$# = 1, csb#$PORT_NUM$# = #$PORT_NUM$#
-  always @ (negedge clk#$PORT_NUM$#)
-  begin : MEM_READ#$PORT_NUM$#
-#<WRITE
-    if (!csb#$PORT_NUM$#_reg && web#$PORT_NUM$#_reg)
-#>WRITE
-#<NO_WRITE
-    if (!csb#$PORT_NUM$#_reg)
-#>NO_WRITE
-       dout#$PORT_NUM$# <= #(DELAY) mem[addr#$PORT_NUM$#_reg];
-  end
-#>R_BLOCK
-endmodule

compiler/characterizer/cacti.py

@@ -51,7 +51,7 @@ class cacti(simulation):
             debug.warning("In analytical mode, all ports have the timing of the first read port.")
             
         # Probe set to 0th bit, does not matter for analytical delay.
-        self.set_probe('0' * self.addr_size, 0)
+        self.set_probe('0' * self.bank_addr_size, 0)
         self.create_graph()
         self.set_internal_spice_names()
         self.create_measurement_names()
@@ -119,4 +119,4 @@ class cacti(simulation):
         debug.info(1, "Leakage Power: {0} mW".format(power.leakage))
         return power
         
-    
+    

compiler/characterizer/delay.py

@@ -342,7 +342,7 @@ class delay(simulation):
         except ValueError:
             debug.error("Probe Address is not of binary form: {0}".format(self.probe_address), 1)
 
-        if len(self.probe_address) != self.addr_size:
+        if len(self.probe_address) != self.bank_addr_size:
             debug.error("Probe Address's number of bits does not correspond to given SRAM", 1)
 
         if not isinstance(self.probe_data, int) or self.probe_data>self.word_size or self.probe_data<0:
@@ -455,7 +455,7 @@ class delay(simulation):
                 self.stim.gen_constant(sig_name="{0}{1}_{2} ".format(self.din_name, write_port, i),
                                        v_val=0)
         for port in self.all_ports:
-            for i in range(self.addr_size):
+            for i in range(self.bank_addr_size):
                 self.stim.gen_constant(sig_name="{0}{1}_{2}".format(self.addr_name, port, i),
                                        v_val=0)
 
@@ -1391,7 +1391,7 @@ class delay(simulation):
         """
 
         for port in self.all_ports:
-            for i in range(self.addr_size):
+            for i in range(self.bank_addr_size):
                 sig_name = "{0}{1}_{2}".format(self.addr_name, port, i)
                 self.stim.gen_pwl(sig_name, self.cycle_times, self.addr_values[port][i], self.period, self.slew, 0.05)
 

compiler/characterizer/elmore.py

@@ -45,7 +45,7 @@ class elmore(simulation):
             debug.warning("In analytical mode, all ports have the timing of the first read port.")
 
         # Probe set to 0th bit, does not matter for analytical delay.
-        self.set_probe('0' * self.addr_size, 0)
+        self.set_probe('0' * self.bank_addr_size, 0)
         self.create_graph()
         self.set_internal_spice_names()
         self.create_measurement_names()
@@ -106,4 +106,4 @@ class elmore(simulation):
         power.leakage /= 1e6
         debug.info(1, "Dynamic Power: {0} mW".format(power.dynamic))
         debug.info(1, "Leakage Power: {0} mW".format(power.leakage))
-        return power
+        return power

compiler/characterizer/functional.py

@@ -60,7 +60,7 @@ class functional(simulation):
             self.addr_spare_index = -int(math.log(self.words_per_row) / math.log(2))
         else:
             # This will select the entire address when one word per row
-            self.addr_spare_index = self.addr_size
+            self.addr_spare_index = self.bank_addr_size
         # If trim is set, specify the valid addresses
         self.valid_addresses = set()
         self.max_address = self.num_rows * self.words_per_row - 1
@@ -68,7 +68,7 @@ class functional(simulation):
             for i in range(self.words_per_row):
                 self.valid_addresses.add(i)
                 self.valid_addresses.add(self.max_address - i - 1)
-        self.probe_address, self.probe_data = '0' * self.addr_size, 0
+        self.probe_address, self.probe_data = '0' * self.bank_addr_size, 0
         self.set_corner(corner)
         self.set_spice_constants()
         self.set_stimulus_variables()
@@ -142,7 +142,7 @@ class functional(simulation):
         r_ops = ["noop", "read"]
 
         # First cycle idle is always an idle cycle
-        comment = self.gen_cycle_comment("noop", "0" * self.word_size, "0" * self.addr_size, "0" * self.num_wmasks, 0, self.t_current)
+        comment = self.gen_cycle_comment("noop", "0" * self.word_size, "0" * self.bank_addr_size, "0" * self.num_wmasks, 0, self.t_current)
         self.add_noop_all_ports(comment)
 
 
@@ -244,7 +244,7 @@ class functional(simulation):
             self.t_current += self.period
 
         # Last cycle idle needed to correctly measure the value on the second to last clock edge
-        comment = self.gen_cycle_comment("noop", "0" * self.word_size, "0" * self.addr_size, "0" * self.num_wmasks, 0, self.t_current)
+        comment = self.gen_cycle_comment("noop", "0" * self.word_size, "0" * self.bank_addr_size, "0" * self.num_wmasks, 0, self.t_current)
         self.add_noop_all_ports(comment)
 
     def gen_masked_data(self, old_word, word, wmask):
@@ -366,7 +366,7 @@ class functional(simulation):
             random_value = random.sample(self.valid_addresses, 1)[0]
         else:
             random_value = random.randint(0, self.max_address)
-        addr_bits = binary_repr(random_value, self.addr_size)
+        addr_bits = binary_repr(random_value, self.bank_addr_size)
         return addr_bits
 
     def get_data(self):
@@ -426,7 +426,7 @@ class functional(simulation):
 
         # Generate address bits
         for port in self.all_ports:
-            for bit in range(self.addr_size):
+            for bit in range(self.bank_addr_size):
                 sig_name="{0}{1}_{2} ".format(self.addr_name, port, bit)
                 self.stim.gen_pwl(sig_name, self.cycle_times, self.addr_values[port][bit], self.period, self.slew, 0.05)
 

compiler/characterizer/simulation.py

@@ -20,7 +20,7 @@ class simulation():
 
         self.name = self.sram.name
         self.word_size = self.sram.word_size
-        self.addr_size = self.sram.addr_size
+        self.bank_addr_size = self.sram.bank_addr_size
         self.write_size = self.sram.write_size
         self.num_spare_rows = self.sram.num_spare_rows
         if not self.sram.num_spare_cols:
@@ -80,7 +80,7 @@ class simulation():
         self.dout_name = "dout"
         self.pins = self.gen_pin_names(port_signal_names=(self.addr_name, self.din_name, self.dout_name),
                                        port_info=(len(self.all_ports), self.write_ports, self.read_ports),
-                                       abits=self.addr_size,
+                                       abits=self.bank_addr_size,
                                        dbits=self.word_size + self.num_spare_cols)
         debug.check(len(self.sram.pins) == len(self.pins),
                     "Number of pins generated for characterization \
@@ -103,7 +103,7 @@ class simulation():
         self.spare_wen_value = {port: [] for port in self.write_ports}
 
         # Three dimensional list to handle each addr and data bits for each port over the number of checks
-        self.addr_values = {port: [[] for bit in range(self.addr_size)] for port in self.all_ports}
+        self.addr_values = {port: [[] for bit in range(self.bank_addr_size)] for port in self.all_ports}
         self.data_values = {port: [[] for bit in range(self.word_size + self.num_spare_cols)] for port in self.write_ports}
         self.wmask_values = {port: [[] for bit in range(self.num_wmasks)] for port in self.write_ports}
         self.spare_wen_values = {port: [[] for bit in range(self.num_spare_cols)] for port in self.write_ports}
@@ -174,10 +174,10 @@ class simulation():
 
     def add_address(self, address, port):
         """ Add the array of address values """
-        debug.check(len(address)==self.addr_size, "Invalid address size.")
+        debug.check(len(address)==self.bank_addr_size, "Invalid address size.")
 
         self.addr_value[port].append(address)
-        bit = self.addr_size - 1
+        bit = self.bank_addr_size - 1
         for c in address:
             if c=="0":
                 self.addr_values[port][bit].append(0)
@@ -330,7 +330,7 @@ class simulation():
         try:
             self.add_address(self.addr_value[port][-1], port)
         except:
-            self.add_address("0" * self.addr_size, port)
+            self.add_address("0" * self.bank_addr_size, port)
 
         # If the port is also a readwrite then add
         # the same value as previous cycle

compiler/modules/bank.py

@@ -93,7 +93,7 @@ class bank(design.design):
             for bit in range(self.word_size + self.num_spare_cols):
                 self.add_pin("din{0}_{1}".format(port, bit), "INPUT")
         for port in self.all_ports:
-            for bit in range(self.addr_size):
+            for bit in range(self.bank_addr_size):
                 self.add_pin("addr{0}_{1}".format(port, bit), "INPUT")
 
         # For more than one bank, we have a bank select and name
@@ -326,11 +326,11 @@ class bank(design.design):
         
         self.row_addr_size = ceil(log(self.num_rows, 2))
         self.col_addr_size = int(log(self.words_per_row, 2))
-        self.addr_size = self.col_addr_size + self.row_addr_size
+        self.bank_addr_size = self.col_addr_size + self.row_addr_size
 
         debug.check(self.num_rows_temp * self.num_cols * self.num_banks ==self.word_size * self.num_words,
                     "Invalid bank sizes.")
-        debug.check(self.addr_size==self.col_addr_size + self.row_addr_size,
+        debug.check(self.bank_addr_size==self.col_addr_size + self.row_addr_size,
                     "Invalid address break down.")
 
         # The order of the control signals on the control bus:

compiler/sram/sram_1bank.py

@@ -57,7 +57,7 @@ class sram_1bank(design, verilog, lef):
             for bit in range(self.word_size + self.num_spare_cols):
                 self.add_pin("din{0}[{1}]".format(port, bit), "INPUT")
         for port in self.all_ports:
-            for bit in range(self.addr_size):
+            for bit in range(self.bank_addr_size):
                 self.add_pin("addr{0}[{1}]".format(port, bit), "INPUT")
 
         # These are used to create the physical pins
@@ -377,7 +377,7 @@ class sram_1bank(design, verilog, lef):
         """ Compute the independent bus widths shared between two and four bank SRAMs """
 
         # address size + control signals + one-hot bank select signals
-        self.num_vertical_line = self.addr_size + self.control_size + 1# + log(self.num_banks, 2) + 1
+        self.num_vertical_line = self.bank_addr_size + self.control_size + 1# + log(self.num_banks, 2) + 1
         # data bus size
         self.num_horizontal_line = self.word_size
 
@@ -419,7 +419,7 @@ class sram_1bank(design, verilog, lef):
                                                                        names=self.control_bus_names[port],
                                                                        length=self.vertical_bus_height)
 
-            self.addr_bus_names=["A{0}[{1}]".format(port, i) for i in range(self.addr_size)]
+            self.addr_bus_names=["A{0}[{1}]".format(port, i) for i in range(self.bank_addr_size)]
             self.vert_control_bus_positions.update(self.create_vertical_pin_bus(layer="m2",
                                                                                 pitch=self.m2_pitch,
                                                                                 offset=self.addr_bus_offset,

compiler/sram/sram_base.py

@@ -50,7 +50,7 @@ class sram_base(design, verilog, lef):
                 self.add_pin("din{0}[{1}]".format(port, bit), "INPUT")
 
         for port in self.all_ports:
-            for bit in range(self.addr_size):
+            for bit in range(self.bank_addr_size):
                 self.add_pin("addr{0}[{1}]".format(port, bit), "INPUT")
 
         # These are used to create the physical pins
@@ -374,7 +374,7 @@ class sram_base(design, verilog, lef):
         """ Compute the independent bus widths shared between two and four bank SRAMs """
 
         # address size + control signals + one-hot bank select signals
-        self.num_vertical_line = self.addr_size + self.control_size + log(self.num_banks, 2) + 1
+        self.num_vertical_line = self.bank_addr_size + self.control_size + log(self.num_banks, 2) + 1
         # data bus size
         self.num_horizontal_line = self.word_size
 
@@ -416,7 +416,7 @@ class sram_base(design, verilog, lef):
                                                                        names=self.control_bus_names[port],
                                                                        length=self.vertical_bus_height)
 
-            self.addr_bus_names=["A{0}[{1}]".format(port, i) for i in range(self.addr_size)]
+            self.addr_bus_names=["A{0}[{1}]".format(port, i) for i in range(self.bank_addr_size)]
             self.vert_control_bus_positions.update(self.create_vertical_pin_bus(layer="m2",
                                                                                 pitch=self.m2_pitch,
                                                                                 offset=self.addr_bus_offset,

compiler/sram/sram_config.py

@@ -121,8 +121,7 @@ class sram_config:
         self.row_addr_size = ceil(log(self.num_rows, 2))
         self.col_addr_size = int(log(self.words_per_row, 2))
         self.bank_addr_size = self.col_addr_size + self.row_addr_size
-        #self.addr_size = self.bank_addr_size + int(log(self.num_banks, 2))
+        self.addr_size = self.bank_addr_size + int(log(self.num_banks, 2))
-        self.addr_size = self.bank_addr_size
         debug.info(1, "Row addr size: {}".format(self.row_addr_size)
                    + " Col addr size: {}".format(self.col_addr_size)
                    + " Bank addr size: {}".format(self.bank_addr_size))

compiler/sram/sram_multibank.py

@@ -21,7 +21,7 @@ class sram_multibank:
             'w_ports': w_ports,
             'banks': list(range(sram.num_banks)),
             'data_width': sram.word_size,
-            'addr_width': sram.addr_size + ceil(log(sram.num_banks, 2)),
+            'addr_width': sram.bank_addr_size + ceil(log(sram.num_banks, 2)),
             'bank_sel': ceil(log(sram.num_banks, 2)),
             'num_wmask': sram.num_wmasks
             }