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Add multiple process corners. Unit tests use nominal corner only. Add fake SCMOS nominal models, but they are broken.

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This commit is contained in:
Matt Guthaus
2018-02-12 09:33:23 -08:00
parent 1795dc5677
commit a12ebeed9f
15 changed files with 77 additions and 31 deletions
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technology/freepdk45/tech/tech.py
+9 -4
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@@ -239,16 +239,21 @@ spice["nmos"] = "nmos_vtg"
spice["pmos"] = "pmos_vtg"
# This is a map of corners to model files
SPICE_MODEL_DIR=os.environ.get("SPICE_MODEL_DIR")
spice["fet_models"] = { "TT" : [SPICE_MODEL_DIR+"/NMOS_VTG.inc",SPICE_MODEL_DIR+"/PMOS_VTG.inc"]}
spice["fet_models"] = { "TT" : [SPICE_MODEL_DIR+"/models_nom/PMOS_VTG.inc",SPICE_MODEL_DIR+"/models_nom/NMOS_VTG.inc"],
"FF" : [SPICE_MODEL_DIR+"/models_ff/PMOS_VTG.inc",SPICE_MODEL_DIR+"/models_ff/NMOS_VTG.inc"],
"SF" : [SPICE_MODEL_DIR+"/models_ss/PMOS_VTG.inc",SPICE_MODEL_DIR+"/models_ff/NMOS_VTG.inc"],
"FS" : [SPICE_MODEL_DIR+"/models_ff/PMOS_VTG.inc",SPICE_MODEL_DIR+"/models_ss/NMOS_VTG.inc"],
"SS" : [SPICE_MODEL_DIR+"/models_ss/PMOS_VTG.inc",SPICE_MODEL_DIR+"/models_ss/NMOS_VTG.inc"]}
#spice stimulus related variables
spice["feasible_period"] = 5 # estimated feasible period in ns
spice["supply_voltage"] = 1.0 # ideal vdd in [Volts]
spice["feasible_period"] = 5 # estimated feasible period in ns
spice["supply_voltages"] = [0.9, 1.0, 1.1] # Supply voltage corners in [Volts]
spice["rise_time"] = 0.005 # rise time in [Nano-seconds]
spice["fall_time"] = 0.005 # fall time in [Nano-seconds]
spice["nom_corner"] = ("TT", 1.0, 25) # Nominal process corner
spice["temperatures"] = [0, 25, 100] # Temperature corners (celcius)
#sram signal names
#FIXME: We don't use these everywhere...
spice["vdd_name"] = "vdd"
spice["gnd_name"] = "gnd"
spice["control_signals"] = ["CSb", "WEb", "OEb"]
technology/scn3me_subm/models/nom/nmos.sp
+12
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@@ -0,0 +1,12 @@
*********************************************
* Transistor Models
* Note: These models are approximate
* and should be substituted with actual
* models from MOSIS or SCN3ME
*********************************************
.MODEL NFET NMOS (LEVEL=3 VTO=0.669845 KP=113.7771E-6
+ NSUB=6E16 U0=458 VFB=-0.851 GAMMA=0.5705 TOX=13.9n
+ TNOM=27)
technology/scn3me_subm/models/nom/pmos.sp
+11
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@@ -0,0 +1,11 @@
*********************************************
* Transistor Models
* Note: These models are approximate
* and should be substituted with actual
* models from MOSIS or SCN3ME
*********************************************
.MODEL PFET PMOS (LEVEL=3 VTO=-0.921340 KP=366.0244-6
+ NSUB=6E16 U0=212 VFB=0.395 GAMMA=0.2370 TOX=13.9n
+ TNOM=27)
technology/scn3me_subm/tech/tech.py
+11 -3
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@@ -199,16 +199,24 @@ spice["nmos"]="n"
spice["pmos"]="p"
# This is a map of corners to model files
SPICE_MODEL_DIR=os.environ.get("SPICE_MODEL_DIR")
spice["fet_models"] = { "TT" : [SPICE_MODEL_DIR+"/on_c5n.sp"] }
# FIXME: Uncomment when we have the new spice models
spice["fet_models"] = { "TT" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"/nom/nmos.sp"] }
# spice["fet_models"] = { "TT" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"/nom/nmos.sp"],
# "FF" : [SPICE_MODEL_DIR+"/ff/pmos.sp",SPICE_MODEL_DIR+"/ff/nmos.sp"],
# "FS" : [SPICE_MODEL_DIR+"/ff/pmos.sp",SPICE_MODEL_DIR+"/ss/nmos.sp"],
# "SF" : [SPICE_MODEL_DIR+"/ss/pmos.sp",SPICE_MODEL_DIR+"/ff/nmos.sp"],
# "SS" : [SPICE_MODEL_DIR+"/ss/pmos.sp",SPICE_MODEL_DIR+"/ss/nmos.sp"] }
#spice stimulus related variables
spice["feasible_period"] = 5 # estimated feasible period in ns
spice["supply_voltage"] = 5.0 # ideal vdd in [Volts]
spice["supply_voltages"] = [4.5, 5.0, 5.5] # Supply voltage corners in [Volts]
spice["rise_time"] = 0.05 # rise time in [Nano-seconds]
spice["fall_time"] = 0.05 # fall time in [Nano-seconds]
spice["nom_corner"] = ("TT", 5.0, 25) # Nominal process corner
spice["temperatures"] = [0, 25, 100] # Temperature corners (celcius)
#sram signal names
#FIXME: We don't use these everywhere...
spice["vdd_name"] = "vdd"
spice["gnd_name"] = "gnd"
spice["control_signals"] = ["CSb", "WEb", "OEb"]
technology/setup_scripts/setup_openram_freepdk45.py
+1 -1
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@@ -32,7 +32,7 @@ os.environ["DRCLVS_HOME"] = DRCLVS_HOME
# SPICE_MODEL_DIR = os.path.abspath(os.environ.get("SPICE_MODEL_DIR"))
# except:
# Always use the one in the PDK dir for FreePDK45
os.environ["SPICE_MODEL_DIR"] = PDK_DIR+"/ncsu_basekit/models/hspice/tran_models/models_nom"
os.environ["SPICE_MODEL_DIR"] = PDK_DIR+"/ncsu_basekit/models/hspice/tran_models"
##########################
#Paths required for OPENRAM to function
technology/setup_scripts/setup_openram_scn3me_subm.py
+4 -4
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@@ -27,10 +27,10 @@ except:
DRCLVS_HOME=OPENRAM_TECH+"/scn3me_subm/tech"
os.environ["DRCLVS_HOME"] = DRCLVS_HOME
try:
SPICE_MODEL_DIR = os.path.abspath(os.environ.get("SPICE_MODEL_DIR"))
except:
os.environ["SPICE_MODEL_DIR"] = "/mada/software/techfiles/scn3me_subm"
# try:
# SPICE_MODEL_DIR = os.path.abspath(os.environ.get("SPICE_MODEL_DIR"))
# except:
os.environ["SPICE_MODEL_DIR"] = OPENRAM_TECH+"/models"
##########################
# Paths required for OPENRAM to function