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Add multiple process corners. Unit tests use nominal corner only. Add fake SCMOS nominal models, but they are broken.

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Matt Guthaus
2018-02-12 09:33:23 -08:00
parent 1795dc5677
commit a12ebeed9f
15 changed files with 77 additions and 31 deletions
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compiler/tests/21_hspice_delay_test.py
+2 -1
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@@ -43,7 +43,8 @@ class timing_sram_test(openram_test):
probe_data = s.word_size - 1
debug.info(1, "Probe address {0} probe data {1}".format(probe_address, probe_data))
d = delay.delay(s,tempspice,tech.spice["nom_corner"])
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
d = delay.delay(s,tempspice,corner)
import tech
loads = [tech.spice["msflop_in_cap"]*4]
slews = [tech.spice["rise_time"]*2]
compiler/tests/21_hspice_setuphold_test.py
+2 -1
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@@ -31,7 +31,8 @@ class timing_setup_test(openram_test):
import tech
slews = [tech.spice["rise_time"]*2]
sh = setup_hold.setup_hold(tech.spice["nom_corner"])
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
sh = setup_hold.setup_hold(corner)
data = sh.analyze(slews,slews)
if OPTS.tech_name == "freepdk45":
compiler/tests/21_ngspice_delay_test.py
+2 -1
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@@ -41,7 +41,8 @@ class timing_sram_test(openram_test):
probe_data = s.word_size - 1
debug.info(1, "Probe address {0} probe data {1}".format(probe_address, probe_data))
d = delay.delay(s,tempspice,tech.spice["nom_corner"])
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
d = delay.delay(s,tempspice,corner)
import tech
loads = [tech.spice["msflop_in_cap"]*4]
slews = [tech.spice["rise_time"]*2]
compiler/tests/21_ngspice_setuphold_test.py
+2 -1
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@@ -30,7 +30,8 @@ class timing_setup_test(openram_test):
import tech
slews = [tech.spice["rise_time"]*2]
sh = setup_hold.setup_hold(tech.spice["nom_corner"])
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
sh = setup_hold.setup_hold(corner)
data = sh.analyze(slews,slews)
if OPTS.tech_name == "freepdk45":
compiler/tests/22_sram_func_test.py
+2 -1
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@@ -43,7 +43,8 @@ class sram_func_test(openram_test):
probe_data = s.word_size - 1
debug.info(1, "Probe address {0} probe data {1}".format(probe_address, probe_data))
d = delay.delay(s,tempspice,tech.spice["nom_corner"])
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
d = delay.delay(s,tempspice,corner)
d.set_probe(probe_address,probe_data)
# This will exit if it doesn't find a feasible period
compiler/tests/config_20_freepdk45.py
+3
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@@ -3,5 +3,8 @@ num_words = 16
num_banks = 1
tech_name = "freepdk45"
process_corners = ["TT"]
supply_voltages = [1.0]
temperatures = [25]
compiler/tests/config_20_scn3me_subm.py
+3
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@@ -3,4 +3,7 @@ num_words = 16
num_banks = 1
tech_name = "scn3me_subm"
process_corners = ["TT"]
supply_voltages = [5.0]
temperatures = [25]