Add multiple process corners. Unit tests use nominal corner only. Add fake SCMOS nominal models, but they are broken.

compiler/characterizer/stimuli.py

@@ -26,8 +26,7 @@ class stimuli():
 
         self.sf = stim_file
         
-        (self.process, self.vdd_voltage, self.temperature) = corner
-        self.gnd_voltage = 0
+        (self.process, self.voltage, self.temperature) = corner
         self.device_models = tech.spice["fet_models"][self.process]
 
     
@@ -158,7 +157,7 @@ class stimuli():
     
         # shift signal times earlier for setup time
         times = np.array(clk_times) - setup*period
-        values = np.array(data_values) * self.vdd_voltage
+        values = np.array(data_values) * self.voltage
         half_slew = 0.5 * slew
         self.sf.write("* (time, data): {}\n".format(zip(clk_times, data_values)))
         self.sf.write("V{0} {0} 0 PWL (0n {1}v ".format(sig_name, values[0]))
@@ -174,10 +173,10 @@ class stimuli():
         self.sf.write("V{0} {0} 0 DC {1}\n".format(sig_name, v_val))
 
     def get_inverse_voltage(self, value):
-        if value > 0.5*self.vdd_voltage:
-            return self.gnd_voltage
-        elif value <= 0.5*self.vdd_voltage:
-            return self.vdd_voltage
+        if value > 0.5*self.voltage:
+            return 0
+        elif value <= 0.5*self.voltage:
+            return self.voltage
         else:
             debug.error("Invalid value to get an inverse of: {0}".format(value))
 
@@ -256,11 +255,11 @@ class stimuli():
 
     def write_supply(self):
         """ Writes supply voltage statements """
-        self.sf.write("V{0} {0} 0.0 {1}\n".format(self.vdd_name, self.vdd_voltage))
-        self.sf.write("V{0} {0} 0.0 {1}\n".format(self.gnd_name, self.gnd_voltage))
+        self.sf.write("V{0} {0} 0.0 {1}\n".format(self.vdd_name, self.voltage))
+        self.sf.write("V{0} {0} 0.0 {1}\n".format(self.gnd_name, 0))
         # This is for the test power supply
-        self.sf.write("V{0} {0} 0.0 {1}\n".format("test"+self.vdd_name, self.vdd_voltage))
-        self.sf.write("V{0} {0} 0.0 {1}\n".format("test"+self.gnd_name, self.gnd_voltage))
+        self.sf.write("V{0} {0} 0.0 {1}\n".format("test"+self.vdd_name, self.voltage))
+        self.sf.write("V{0} {0} 0.0 {1}\n".format("test"+self.gnd_name, 0))
 
 
     def run_sim(self):

compiler/globals.py

@@ -291,11 +291,11 @@ def import_tech():
     import tech
     # Set some default options now based on the technology...
     if (OPTS.process_corners == ""):
-        OPTS.process_corners = [tech.spice["nom_corner"][0]]
+        OPTS.process_corners = tech.spice["fet_models"].keys()
     if (OPTS.supply_voltages == ""):
-        OPTS.supply_voltages = [tech.spice["nom_corner"][1]]
+        OPTS.supply_voltages = tech.spice["supply_voltages"]
     if (OPTS.temperatures == ""):
-        OPTS.temperatures = [tech.spice["nom_corner"][2]]
+        OPTS.temperatures = tech.spice["temperatures"]
 
 
 def print_time(name, now_time, last_time=None):

compiler/tests/21_hspice_delay_test.py

@@ -43,7 +43,8 @@ class timing_sram_test(openram_test):
         probe_data = s.word_size - 1
         debug.info(1, "Probe address {0} probe data {1}".format(probe_address, probe_data))
 
-        d = delay.delay(s,tempspice,tech.spice["nom_corner"])
+        corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
+        d = delay.delay(s,tempspice,corner)
         import tech
         loads = [tech.spice["msflop_in_cap"]*4]
         slews = [tech.spice["rise_time"]*2]

compiler/tests/21_hspice_setuphold_test.py

@@ -31,7 +31,8 @@ class timing_setup_test(openram_test):
         import tech
         slews = [tech.spice["rise_time"]*2]
         
-        sh = setup_hold.setup_hold(tech.spice["nom_corner"])
+        corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
+        sh = setup_hold.setup_hold(corner)
         data = sh.analyze(slews,slews)
 
         if OPTS.tech_name == "freepdk45":

compiler/tests/21_ngspice_delay_test.py

@@ -41,7 +41,8 @@ class timing_sram_test(openram_test):
         probe_data = s.word_size - 1
         debug.info(1, "Probe address {0} probe data {1}".format(probe_address, probe_data))
 
-        d = delay.delay(s,tempspice,tech.spice["nom_corner"])
+        corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
+        d = delay.delay(s,tempspice,corner)
         import tech
         loads = [tech.spice["msflop_in_cap"]*4]
         slews = [tech.spice["rise_time"]*2]

compiler/tests/21_ngspice_setuphold_test.py

@@ -30,7 +30,8 @@ class timing_setup_test(openram_test):
         import tech
         slews = [tech.spice["rise_time"]*2]
         
-        sh = setup_hold.setup_hold(tech.spice["nom_corner"])
+        corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
+        sh = setup_hold.setup_hold(corner)
         data = sh.analyze(slews,slews)
 
         if OPTS.tech_name == "freepdk45":

compiler/tests/22_sram_func_test.py

@@ -43,7 +43,8 @@ class sram_func_test(openram_test):
         probe_data = s.word_size - 1
         debug.info(1, "Probe address {0} probe data {1}".format(probe_address, probe_data))
 
-        d = delay.delay(s,tempspice,tech.spice["nom_corner"])
+        corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
+        d = delay.delay(s,tempspice,corner)
         d.set_probe(probe_address,probe_data)
 
         # This will exit if it doesn't find a feasible period

compiler/tests/config_20_freepdk45.py

@@ -3,5 +3,8 @@ num_words = 16
 num_banks = 1
 
 tech_name = "freepdk45"
+process_corners = ["TT"]
+supply_voltages = [1.0]
+temperatures = [25]
 
 

compiler/tests/config_20_scn3me_subm.py

@@ -3,4 +3,7 @@ num_words = 16
 num_banks = 1
 
 tech_name = "scn3me_subm"
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]