mirror of https://github.com/VLSIDA/OpenRAM.git
Add vdd/gnd pins to the side.
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@ -11,7 +11,7 @@ process_corners = ["TT"]
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supply_voltages = [5.0]
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supply_voltages = [5.0]
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temperatures = [25]
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temperatures = [25]
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route_supplies = True
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route_supplies = "side"
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check_lvsdrc = True
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check_lvsdrc = True
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output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
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output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,
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@ -1214,7 +1214,7 @@ class router(router_tech):
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return self.convert_track_to_pin(v)
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return self.convert_track_to_pin(v)
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return None
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return None
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def get_ll_pin(self, pin_name):
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def get_ll_pin(self, pin_name):
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""" Return the lowest, leftest pin group """
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""" Return the lowest, leftest pin group """
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@ -1228,6 +1228,23 @@ class router(router_tech):
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keep_pin = pin
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keep_pin = pin
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return keep_pin
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return keep_pin
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def get_left_pins(self, pin_name):
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""" Return the leftest pin(s) group """
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keep_pins = []
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for index, pg in enumerate(self.pin_groups[pin_name]):
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for pin in pg.enclosures:
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if not keep_pins:
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keep_pins = [pin]
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else:
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# Only need to check first since they are all the same left value
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if pin.lx() == keep_pins[0].lx():
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keep_pins.append(pin)
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elif pin.lx() < keep_pins[0].lx():
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keep_pins = [pin]
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return keep_pins
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def check_all_routed(self, pin_name):
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def check_all_routed(self, pin_name):
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"""
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"""
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@ -229,6 +229,10 @@ class sram_base(design, verilog, lef):
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if not OPTS.route_supplies:
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if not OPTS.route_supplies:
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# Do not route the power supply (leave as must-connect pins)
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# Do not route the power supply (leave as must-connect pins)
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return
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return
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elif OPTS.route_supplies == "grid":
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from supply_grid_router import supply_grid_router as router
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else:
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from supply_tree_router import supply_tree_router as router
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try:
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try:
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from tech import power_grid
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from tech import power_grid
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@ -237,17 +241,15 @@ class sram_base(design, verilog, lef):
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# if no power_grid is specified by tech we use sensible defaults
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# if no power_grid is specified by tech we use sensible defaults
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# Route a M3/M4 grid
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# Route a M3/M4 grid
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grid_stack = self.m3_stack
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grid_stack = self.m3_stack
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if OPTS.route_supplies == "grid":
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from supply_grid_router import supply_grid_router as router
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elif OPTS.route_supplies:
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from supply_tree_router import supply_tree_router as router
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rtr=router(grid_stack, self)
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rtr=router(grid_stack, self)
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rtr.route()
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rtr.route()
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lowest_coord = self.find_lowest_coords()
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highest_coord = self.find_highest_coords()
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# Find the lowest leftest pin for vdd and gnd
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# Find the lowest leftest pin for vdd and gnd
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for pin_name in ["vdd", "gnd"]:
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for (pin_name, pin_index) in [("vdd", 0), ("gnd", 1)]:
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# Copy the pin shape(s) to rectangles
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# Copy the pin shape(s) to rectangles
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for pin in self.get_pins(pin_name):
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for pin in self.get_pins(pin_name):
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self.add_rect(pin.layer,
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self.add_rect(pin.layer,
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@ -258,23 +260,57 @@ class sram_base(design, verilog, lef):
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# Remove the pin shape(s)
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# Remove the pin shape(s)
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self.remove_layout_pin(pin_name)
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self.remove_layout_pin(pin_name)
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# Get the lowest, leftest pin
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# Either add two long rails or a simple pin
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pin = rtr.get_ll_pin(pin_name)
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if OPTS.route_supplies == "side":
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# Get the leftest pins
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pins = rtr.get_left_pins(pin_name)
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pin_width = 2 * getattr(self, "{}_width".format(pins[0].layer))
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pin_space = 2 * getattr(self, "{}_space".format(pins[0].layer))
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supply_pitch = pin_width + pin_space
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# Add side power rails on left from bottom to top
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# These have a temporary name and will be connected later.
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# They are here to reserve space now and ensure other pins go beyond
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# their perimeter.
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supply_height = highest_coord.y - lowest_coord.y
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supply_pin = self.add_layout_pin(text=pin_name,
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layer="m4",
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offset=lowest_coord + vector(pin_index * supply_pitch, 0),
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width=pin_width,
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height=supply_height)
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# Add it as an IO pin to the perimeter
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route_width = pins[0].rx() - lowest_coord.x
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lowest_coord = self.find_lowest_coords()
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for pin in pins:
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route_width = pin.rx() - lowest_coord.x
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pin_offset = vector(lowest_coord.x, pin.by())
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pin_width = 2 * getattr(self, "{}_width".format(pin.layer))
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self.add_rect(pin.layer,
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pin_offset = vector(lowest_coord.x, pin.by())
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pin_offset,
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self.add_layout_pin(pin_name,
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route_width,
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pin.layer,
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pin.height())
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pin_offset,
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center_offset = vector(supply_pin.cx(),
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pin_width,
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pin.cy())
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pin.height())
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self.add_via_center(layers=self.m3_stack,
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self.add_rect(pin.layer,
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offset=center_offset)
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pin_offset,
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else:
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route_width,
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# Get the lowest, leftest pin
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pin.height())
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pin = rtr.get_ll_pins(pin_name)
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pin_width = 2 * getattr(self, "{}_width".format(pin.layer))
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pin_space = 2 * getattr(self, "{}_space".format(pin.layer))
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# Add it as an IO pin to the perimeter
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route_width = pin.rx() - lowest_coord.x
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pin_offset = vector(lowest_coord.x, pin.by())
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self.add_rect(pin.layer,
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pin_offset,
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route_width,
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pin.height())
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self.add_layout_pin(pin_name,
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pin.layer,
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pin_offset,
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pin_width,
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pin.height())
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def route_escape_pins(self):
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def route_escape_pins(self):
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"""
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"""
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