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Merge branch 'multiport' into supply_routing

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This commit is contained in:
Matt Guthaus
2018-10-11 09:56:38 -07:00
parent 823cb04b80 e22e658090
commit a094db9077
23 changed files with 330 additions and 330 deletions
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compiler/bitcells/bitcell.py
+3 -3
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@@ -38,9 +38,9 @@ class bitcell(design.design):
def list_bitcell_pins(self, col, row):
""" Creates a list of connections in the bitcell, indexed by column and row, for instance use in bitcell_array """
bitcell_pins = ["bl[{0}]".format(col),
"br[{0}]".format(col),
"wl[{0}]".format(row),
bitcell_pins = ["bl_{0}".format(col),
"br_{0}".format(col),
"wl_{0}".format(row),
"vdd",
"gnd"]
return bitcell_pins
compiler/bitcells/pbitcell.py
+4 -4
View File
@@ -1186,10 +1186,10 @@ class pbitcell(design.design):
""" Creates a list of connections in the bitcell, indexed by column and row, for instance use in bitcell_array """
bitcell_pins = []
for port in range(self.total_ports):
bitcell_pins.append("bl{0}[{1}]".format(port,col))
bitcell_pins.append("br{0}[{1}]".format(port,col))
bitcell_pins.append("bl{0}_{1}".format(port,col))
bitcell_pins.append("br{0}_{1}".format(port,col))
for port in range(self.total_ports):
bitcell_pins.append("wl{0}[{1}]".format(port,row))
bitcell_pins.append("wl{0}_{1}".format(port,row))
bitcell_pins.append("vdd")
bitcell_pins.append("gnd")
return bitcell_pins
@@ -1242,4 +1242,4 @@ class pbitcell(design.design):
Q_bar_pos = self.inverter_pmos_left.get_pin("D").uc()
vdd_pos = vector(Q_bar_pos.x, self.vdd_position.y)
self.add_path("metal1", [Q_bar_pos, vdd_pos])
self.add_path("metal1", [Q_bar_pos, vdd_pos])