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Added netlist only configuration option.

This commit is contained in:
Matt Guthaus 2018-08-27 14:33:02 -07:00
parent 19d46f5954
commit 9f051df18d
4 changed files with 27 additions and 13 deletions
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8
compiler/globals.py
View File

@ -204,6 +204,11 @@ def read_config(config_file, is_unit_test=True):
OPTS.is_unit_test=is_unit_test OPTS.is_unit_test=is_unit_test
# If we are only generating a netlist, we can't do DRC/LVS
if OPTS.netlist_only:
OPTS.check_lvsdrc=False
# If config didn't set output name, make a reasonable default. # If config didn't set output name, make a reasonable default.
if (OPTS.output_name == ""): if (OPTS.output_name == ""):
OPTS.output_name = "sram_{0}rw_{1}b_{2}w_{3}bank_{4}".format(OPTS.rw_ports, OPTS.output_name = "sram_{0}rw_{1}b_{2}w_{3}bank_{4}".format(OPTS.rw_ports,
@ -372,6 +377,9 @@ def report_status():
print("Word size: {0}\nWords: {1}\nBanks: {2}".format(OPTS.word_size, print("Word size: {0}\nWords: {1}\nBanks: {2}".format(OPTS.word_size,
OPTS.num_words, OPTS.num_words,
OPTS.num_banks)) OPTS.num_banks))
if OPTS.netlist_only:
print("Netlist only mode (no physical design is being done).")
if not OPTS.check_lvsdrc: if not OPTS.check_lvsdrc:
print("DRC/LVS/PEX checking is disabled.") print("DRC/LVS/PEX checking is disabled.")

5
compiler/openram.py
View File

@ -40,7 +40,10 @@ report_status()
import verify import verify
import sram import sram
output_files = ["{0}.{1}".format(OPTS.output_name,x) for x in ["sp","gds","v","lib","lef"]] output_extensions = ["sp","v","lib"]
if not OPTS.netlist_only:
output_extensions.extend(["gds","lef"])
output_files = ["{0}.{1}".format(OPTS.output_name,x) for x in output_extensions]
print("Output files are: ") print("Output files are: ")
print(*output_files,sep="\n") print(*output_files,sep="\n")

2
compiler/options.py
View File

@ -18,6 +18,8 @@ class options(optparse.Values):
# This is the verbosity level to control debug information. 0 is none, 1 # This is the verbosity level to control debug information. 0 is none, 1
# is minimal, etc. # is minimal, etc.
debug_level = 0 debug_level = 0
# When enabled, layout is not generated (and no DRC or LVS are performed)
netlist_only = False
# This determines whether LVS and DRC is checked for each submodule. # This determines whether LVS and DRC is checked for each submodule.
check_lvsdrc = True check_lvsdrc = True
# Variable to select the variant of spice # Variable to select the variant of spice

25
compiler/sram.py
View File

@ -99,19 +99,20 @@ class sram():
lib(out_dir=OPTS.output_path, sram=self.s, sp_file=sp_file) lib(out_dir=OPTS.output_path, sram=self.s, sp_file=sp_file)
print_time("Characterization", datetime.datetime.now(), start_time) print_time("Characterization", datetime.datetime.now(), start_time)
# Write the layout if not OPTS.netlist_only:
start_time = datetime.datetime.now() # Write the layout
gdsname = OPTS.output_path + self.s.name + ".gds" start_time = datetime.datetime.now()
print("GDS: Writing to {0}".format(gdsname)) gdsname = OPTS.output_path + self.s.name + ".gds"
self.s.gds_write(gdsname) print("GDS: Writing to {0}".format(gdsname))
print_time("GDS", datetime.datetime.now(), start_time) self.s.gds_write(gdsname)
print_time("GDS", datetime.datetime.now(), start_time)
# Create a LEF physical model # Create a LEF physical model
start_time = datetime.datetime.now() start_time = datetime.datetime.now()
lefname = OPTS.output_path + self.s.name + ".lef" lefname = OPTS.output_path + self.s.name + ".lef"
print("LEF: Writing to {0}".format(lefname)) print("LEF: Writing to {0}".format(lefname))
self.s.lef_write(lefname) self.s.lef_write(lefname)
print_time("LEF", datetime.datetime.now(), start_time) print_time("LEF", datetime.datetime.now(), start_time)
# Write a verilog model # Write a verilog model
start_time = datetime.datetime.now() start_time = datetime.datetime.now()