Merge branch 'dev' into pex

compiler/sram/sram.py

@@ -90,9 +90,9 @@ class sram():
 
         # Save the LVS file
         start_time = datetime.datetime.now()
-        spname = OPTS.output_path + self.s.name + ".lvs"
-        debug.print_raw("LVS: Writing to {0}".format(spname))
-        self.lvs_write(spname)
+        lvsname = OPTS.output_path + self.s.name + ".lvs.sp"
+        debug.print_raw("LVS: Writing to {0}".format(lvsname))
+        self.lvs_write(lvsname)
         print_time("LVS writing", datetime.datetime.now(), start_time)
         
         # Save the extracted spice file
@@ -100,8 +100,10 @@ class sram():
             import verify
             start_time = datetime.datetime.now()
             # Output the extracted design if requested
-            sp_file = OPTS.output_path + "temp_pex.sp"
-            verify.run_pex(self.s.name, gdsname, spname, output=sp_file)
+            pexname = OPTS.output_path + self.s.name + ".pex.sp"
+            spname = OPTS.output_path + self.s.name + ".sp"
+            verify.run_pex(self.s.name, gdsname, spname, output=pexname)
+            sp_file = pexname
             print_time("Extraction", datetime.datetime.now(), start_time)
         else:
             # Use generated spice file for characterization

compiler/sram/sram_1bank.py

@@ -160,7 +160,10 @@ class sram_1bank(sram_base):
         port = 0
         # Add the col address flops below the bank to the right of the control logic
         x_offset = self.control_logic_insts[port].rx() + self.dff.width
-        y_offset = - self.data_bus_size[port] - self.dff.height
+        # Place it a data bus below the x-axis, but at least as low as the control logic to not block
+        # the control logic signals
+        y_offset = min(-self.data_bus_size[port] - self.dff.height,
+                       self.control_logic_insts[port].by())
         if self.col_addr_dff:
             self.col_addr_pos[port] = vector(x_offset,
                                              y_offset)
@@ -201,7 +204,10 @@ class sram_1bank(sram_base):
             
             # Add the col address flops below the bank to the right of the control logic
             x_offset = self.control_logic_insts[port].lx() - 2 * self.dff.width
-            y_offset = self.bank.height + self.data_bus_size[port] + self.dff.height
+            # Place it a data bus below the x-axis, but at least as high as the control logic to not block
+            # the control logic signals
+            y_offset = max(self.bank.height + self.data_bus_size[port] + self.dff.height,
+                           self.control_logic_insts[port].uy() - self.dff.height)
             if self.col_addr_dff:
                 self.col_addr_pos[port] = vector(x_offset,
                                                  y_offset)

compiler/sram/sram_base.py

@@ -414,6 +414,7 @@ class sram_base(design, verilog, lef):
                 temp.append("dout{0}[{1}]".format(port, bit))
         for port in self.all_ports:
             temp.append("rbl_bl{0}".format(port))
+            temp.append("rbl_br{0}".format(port))
         for port in self.write_ports:
             for bit in range(self.word_size + self.num_spare_cols):
                 temp.append("bank_din{0}[{1}]".format(port, bit))