mirror of https://github.com/VLSIDA/OpenRAM.git
bunch of cleanups to core rom classes
This commit is contained in:
SWalker
parent
ddba3b3718
commit
9b99e6c124
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@ -113,7 +113,6 @@ class rom_bank(design,rom_verilog):
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# FIXME: Somehow ROM layout behaves weird and doesn't add all the pin
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# shapes before routing supplies
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init_bbox = self.get_bbox()
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if OPTS.route_supplies:
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self.route_supplies(init_bbox)
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# Route the pins to the perimeter
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if OPTS.perimeter_pins:
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@ -368,8 +367,11 @@ class rom_bank(design,rom_verilog):
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# Route precharge to col decoder
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start = prechrg_control.center()
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mid1 = vector(self.control_inst.rx() + self.interconnect_layer_pitch, prechrg_control.cy())
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mid2 = vector(self.control_inst.rx() + self.interconnect_layer_pitch, col_decode_prechrg.cy())
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path_x = self.control_inst.rx() + 1.2 * self.route_layer_pitch
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mid1 = vector(path_x, prechrg_control.cy())
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mid2 = vector(path_x, col_decode_prechrg.cy())
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end = col_decode_prechrg.center()
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self.add_path(self.route_stack[0], [start, mid1, mid2, end])
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@ -378,7 +380,7 @@ class rom_bank(design,rom_verilog):
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offset=end)
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start = mid1
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mid1 = vector(self.control_inst.rx() + self.interconnect_layer_pitch, start.y)
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mid1 = vector(path_x, start.y)
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mid2 = vector(mid1.x, col_decode_clk.cy())
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end = col_decode_clk.center()
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self.add_path(self.route_stack[0], [start, mid1, mid2, end])
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@ -388,6 +390,10 @@ class rom_bank(design,rom_verilog):
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mid = vector(col_decode_prechrg.cx(), array_prechrg.cy() )
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self.add_path(self.route_stack[0], [array_prechrg.center(), mid, col_decode_prechrg.center()])
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self.add_via_stack_center(from_layer=self.route_stack[0],
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to_layer=array_prechrg.layer,
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offset=array_prechrg.center())
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def route_clock(self):
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clk_out = self.control_inst.get_pin("clk_out")
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@ -409,6 +415,10 @@ class rom_bank(design,rom_verilog):
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to_layer=row_decode_clk.layer,
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offset=addr_control_clk)
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self.add_via_stack_center(from_layer=self.route_stack[2],
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to_layer=row_decode_prechrg.layer,
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offset=row_decode_prechrg.center())
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self.add_segment_center(row_decode_clk.layer, addr_control_clk, row_decode_clk.rc())
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def route_array_outputs(self):
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@ -417,7 +427,7 @@ class rom_bank(design,rom_verilog):
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inv_out_pins = [self.bitline_inv_inst.get_pin("out_{}".format(bl)) for bl in range(self.cols)]
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mux_pins = [self.mux_inst.get_pin("bl_{}".format(bl)) for bl in range(self.cols)]
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self.connect_col_pins(self.interconnect_layer, array_out_pins + inv_in_pins, round=True, directions="nonpref")
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self.connect_col_pins(self.route_stack[2], array_out_pins + inv_in_pins, round=True, directions="nonpref")
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self.connect_col_pins(self.interconnect_layer, inv_out_pins + mux_pins, round=True, directions="nonpref")
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def route_output_buffers(self):
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@ -450,6 +460,8 @@ class rom_bank(design,rom_verilog):
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for inst in self.insts:
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self.copy_power_pins(inst, pin_name)
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if OPTS.route_supplies:
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from openram.router import supply_router as router
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rtr = router(layers=self.supply_stack,
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design=self,
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@ -22,7 +22,9 @@ class rom_base_array(bitcell_base_array):
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self.data = bitmap
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self.tap_direction = tap_direction
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self.pitch_match = pitch_match
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# This attribute is redundant with the tap direction
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# TODO: consolidate pitch matching logic to just be based on tap direction
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self.pitch_match = tap_direction == "row"
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self.bitline_layer = bitline_layer
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self.strap_spacing = strap_spacing
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self.wordline_layer = wordline_layer
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@ -89,7 +91,6 @@ class rom_base_array(bitcell_base_array):
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self.poly_tap = factory.create(module_type="rom_poly_tap", add_active_tap=True)
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self.end_poly_tap = factory.create(module_type="rom_poly_tap", place_poly=True)
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print("poly tap width", self.poly_tap.width, "height", self.poly_tap.height, self.tap_direction)
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self.precharge_array = factory.create(module_type="rom_precharge_array",
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cols=self.column_size,
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strap_spacing=self.strap_spacing,
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@ -102,7 +103,6 @@ class rom_base_array(bitcell_base_array):
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self.route_pitch = drc("{0}_to_{0}".format(self.bitline_layer))
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def add_pins(self):
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print(self.get_wordline_names())
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for bl_name in self.get_bitline_names():
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self.add_pin(bl_name, "OUTPUT")
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for wl_name in self.get_wordline_names():
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@ -234,12 +234,10 @@ class rom_base_array(bitcell_base_array):
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bottom = vector(pin.cx(), pin.by())
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top = vector(pin.cx(), gnd_y)
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self.add_via_stack_center(offset=top, from_layer=self.bitline_layer, to_layer=self.supply_stack[0])
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# self.add_via_center(offset=bottom, layers=self.supply_stack)
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self.add_layout_pin_rect_ends(name="gnd", layer=self.supply_stack[0], start=bottom, end=top)
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self.remove_layout_pin("gnd_tmp")
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# self.add_segment_center(layer=self.supply_stack[2], start=vector(min_x, bottom.y), end=vector(max_x, bottom.y))
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self.add_segment_center(layer=self.bitline_layer, start=gnd_l, end=vector(min_x, gnd_l.y))
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self.add_segment_center(layer=self.bitline_layer, start=gnd_r, end=vector(max_x, gnd_r.y))
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@ -333,7 +331,6 @@ class rom_base_array(bitcell_base_array):
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else:
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output_layer = "m3"
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rail_y = self.precharge_inst.get_pins("vdd")[0].cy()
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print("cols ", self.bitline_names[0])
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for bl in range(self.column_size):
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src_pin = self.cell_list[0][bl].get_pin("S")
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@ -80,7 +80,6 @@ class rom_base_cell(design):
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self.cell_inst = self.add_inst( name=self.name + "_nmos",
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mod=self.nmos,
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)
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print("bitmos", self.cell_inst.height, self.cell_inst.width)
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if self.bit_value == 0:
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self.connect_inst(["bl", "wl", "bl", "gnd"])
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@ -231,6 +231,14 @@ class rom_decoder(design):
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self.add_path(self.inv_route_layer, [addr_out_pin.center(), addr_middle, addr_pin.center()])
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self.add_path(self.inv_route_layer, [addr_bar_out_pin.center(), addr_bar_middle, addr_bar_pin.center()])
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self.add_via_stack_center(offset=addr_pin.center(),
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from_layer=addr_pin.layer,
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to_layer=self.inv_route_layer)
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self.add_via_stack_center(offset=addr_bar_pin.center(),
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from_layer=addr_bar_pin.layer,
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to_layer=self.inv_route_layer)
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self.copy_layout_pin(self.buf_inst, "A{}_in".format(i), "A{}".format(i))
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def route_supplies(self):
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@ -35,7 +35,6 @@ class rom_poly_tap(design):
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def create_layout(self):
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self.place_via()
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# self.extend_poly()
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if self.add_tap or self.place_poly:
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self.place_active_tap()
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@ -47,7 +46,6 @@ class rom_poly_tap(design):
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contact_width = self.poly_contact.width
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self.height = self.dummy.height
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self.width = contact_width + self.pitch_offset
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print("pitch off", self.pitch_offset)
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super().add_boundary()
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def place_via(self):
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@ -83,12 +81,9 @@ class rom_poly_tap(design):
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tap_y = self.via.cy() + self.dummy.width * 0.5
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contact_pos = vector(tap_x, tap_y)
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# edge of the next nmos
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active_edge = self.dummy.width - self.dummy.cell_inst.height - self.poly_extend_active
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# edge of the active contact
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tap_edge = tap_x + 0.5 * self.active_contact.height
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self.pitch_offset += (self.active_space * 2) - (tap_edge - active_edge) + self.contact_x_offset
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# This pitch offset is used throughout the memory bank to make sure the pitch of the decoder outputs matches the pitch of the array inputs
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self.pitch_offset = 0.5 * self.active_contact.width + self.active_space + 0.5 * self.contact_width + self.active_enclose_contact
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if self.tx_type == "nmos" and self.add_tap:
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self.add_via_center(layers=self.active_stack,
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@ -24,7 +24,6 @@ class rom_precharge_cell(rom_base_cell):
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self.place_tap()
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self.extend_well()
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print("precharge", self.height, self.width)
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def add_modules(self):
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@ -44,7 +43,6 @@ class rom_precharge_cell(rom_base_cell):
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self.cell_inst = self.add_inst( name="precharge_pmos",
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mod=self.pmos,
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)
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print("premos", self.cell_inst.height, self.cell_inst.width)
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self.connect_inst(["bitline", "gate", "vdd", "vdd"])
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def add_pins(self):
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@ -58,7 +56,6 @@ class rom_precharge_cell(rom_base_cell):
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self.poly_size = (self.cell_inst.width + self.active_space) - (self.cell_inst.height + 2 * self.poly_extend_active)
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def extend_well(self):
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print(self.nwell_enclose_active)
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well_y = self.get_pin("vdd").cy() - 0.5 * self.tap.height - self.nwell_enclose_active
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well_ll = vector(0, well_y)
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height = self.get_pin("D").cy() + self.nwell_enclose_active - well_y
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@ -91,5 +88,4 @@ class rom_precharge_cell(rom_base_cell):
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pass
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def short_gate(self):
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print("not shorting")
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pass
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