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synced 2026-09-07 03:20:39 +02:00
bunch of cleanups to core rom classes
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@@ -24,7 +24,6 @@ class rom_precharge_cell(rom_base_cell):
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self.place_tap()
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self.extend_well()
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print("precharge", self.height, self.width)
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def add_modules(self):
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@@ -44,7 +43,6 @@ class rom_precharge_cell(rom_base_cell):
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self.cell_inst = self.add_inst( name="precharge_pmos",
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mod=self.pmos,
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)
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print("premos", self.cell_inst.height, self.cell_inst.width)
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self.connect_inst(["bitline", "gate", "vdd", "vdd"])
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def add_pins(self):
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@@ -58,7 +56,6 @@ class rom_precharge_cell(rom_base_cell):
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self.poly_size = (self.cell_inst.width + self.active_space) - (self.cell_inst.height + 2 * self.poly_extend_active)
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def extend_well(self):
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print(self.nwell_enclose_active)
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well_y = self.get_pin("vdd").cy() - 0.5 * self.tap.height - self.nwell_enclose_active
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well_ll = vector(0, well_y)
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height = self.get_pin("D").cy() + self.nwell_enclose_active - well_y
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@@ -91,5 +88,4 @@ class rom_precharge_cell(rom_base_cell):
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pass
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def short_gate(self):
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print("not shorting")
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pass
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