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bunch of cleanups to core rom classes
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@@ -80,7 +80,6 @@ class rom_base_cell(design):
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self.cell_inst = self.add_inst( name=self.name + "_nmos",
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mod=self.nmos,
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)
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print("bitmos", self.cell_inst.height, self.cell_inst.width)
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if self.bit_value == 0:
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self.connect_inst(["bl", "wl", "bl", "gnd"])
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