merge conflict

compiler/base/hierarchy_layout.py

@@ -998,8 +998,13 @@ class layout():
         max_x = max([pin.center().x for pin in pins])
         min_x = min([pin.center().x for pin in pins])
 
+        # max_x_lc & min_x_rc are for routing to/from the edge of the pins
+        # to increase spacing between contacts of different nets
+        max_x_lc = max([pin.lc().x for pin in pins])
+        min_x_rc = min([pin.rc().x for pin in pins])
+
         # if we are less than a pitch, just create a non-preferred layer jog
-        if max_x - min_x <= pitch:
+        if max_x_lc - min_x_rc <= pitch:
             half_layer_width = 0.5 * drc["minwidth_{0}".format(self.vertical_layer)]
 
             # Add the horizontal trunk on the vertical layer!
@@ -1020,7 +1025,15 @@ class layout():
 
             # Route each pin to the trunk
             for pin in pins:
-                mid = vector(pin.center().x, trunk_offset.y)
+                # If there is sufficient space, Route from the edge of the pins
+                # Otherwise, route from the center of the pins
+                if max_x_lc - min_x_rc > pitch:
+                    if pin.center().x == max_x:
+                        mid = vector(pin.lc().x, trunk_offset.y)
+                    else:
+                        mid = vector(pin.rc().x, trunk_offset.y)
+                else:
+                    mid = vector(pin.center().x, trunk_offset.y)
                 self.add_path(self.vertical_layer, [pin.center(), mid])
                 self.add_via_center(layers=layer_stack,
                                     offset=mid)
@@ -1037,8 +1050,13 @@ class layout():
         max_y = max([pin.center().y for pin in pins])
         min_y = min([pin.center().y for pin in pins])
 
+        # max_y_bc & min_y_uc are for routing to/from the edge of the pins
+        # to reduce spacing between contacts of different nets
+        max_y_bc = max([pin.bc().y for pin in pins])
+        min_y_uc = min([pin.uc().y for pin in pins])
+
         # if we are less than a pitch, just create a non-preferred layer jog
-        if max_y - min_y <= pitch:
+        if max_y_bc - min_y_uc <= pitch:
 
             half_layer_width = 0.5 * drc["minwidth_{0}".format(self.horizontal_layer)]
 
@@ -1060,7 +1078,15 @@ class layout():
 
             # Route each pin to the trunk
             for pin in pins:
-                mid = vector(trunk_offset.x, pin.center().y)
+                # If there is sufficient space, Route from the edge of the pins
+                # Otherwise, route from the center of the pins
+                if max_y_bc - min_y_uc > pitch:
+                    if pin.center().y == max_y:
+                        mid = vector(trunk_offset.x, pin.bc().y)
+                    else:
+                        mid = vector(trunk_offset.x, pin.uc().y)
+                else:
+                    mid = vector(trunk_offset.x, pin.center().y)
                 self.add_path(self.horizontal_layer, [pin.center(), mid])
                 self.add_via_center(layers=layer_stack,
                                     offset=mid)

compiler/modules/port_data.py

@@ -521,10 +521,10 @@ class port_data(design.design):
 
         insn2_start_bit = 1 if self.port == 0 else 0
 
-        self.connect_bitlines(inst1=inst1,
+        self.channel_route_bitlines(inst1=inst1,
-                              inst2=inst2,
+                                    inst2=inst2,
-                              num_bits=self.num_cols,
+                                    num_bits=self.num_cols,
-                              inst2_start_bit=insn2_start_bit)
+                                    inst2_start_bit=insn2_start_bit)
 
     def route_sense_amp_to_column_mux_or_precharge_array(self, port):
         """ Routing of BL and BR between sense_amp and column mux or precharge array """
@@ -743,4 +743,3 @@ class port_data(design.design):
         """Precharge adds a loop between bitlines, can be excluded to reduce complexity"""
         if self.precharge_array_inst:
             self.graph_inst_exclude.add(self.precharge_array_inst)
-

compiler/pgates/single_level_column_mux.py

@@ -11,7 +11,7 @@ from tech import drc, layer
 from vector import vector
 from sram_factory import factory
 import logical_effort
-
+from utils import round_to_grid
 
 class single_level_column_mux(pgate.pgate):
     """
@@ -75,6 +75,17 @@ class single_level_column_mux(pgate.pgate):
         bl_pos = vector(bl_pin.lx(), 0)
         br_pos = vector(br_pin.lx(), 0)
 
+        # The bitline input/output pins must be a least as wide as the metal pitch
+        #   so that there is enough space to route to/from the pins.
+        # FIXME: bitline_metal_pitch should be greater than the horizontal metal pitch used in port_data
+        bitline_metal_pitch = self.width / 2
+        bitline_width = br_pos.x - bl_pos.x
+        if bitline_width < bitline_metal_pitch:
+            bitline_width_increase_bl = round_to_grid((bitline_metal_pitch - bitline_width) / 2)
+            bitline_width_increase_br = round_to_grid((bitline_metal_pitch - bitline_width) - bitline_width_increase_bl)
+            bl_pos = bl_pos + vector(-bitline_width_increase_bl, 0)
+            br_pos = br_pos + vector( bitline_width_increase_br, 0)
+
         # bl and br
         self.add_layout_pin(text="bl",
                             layer=bl_pin.layer,