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OpenRAM
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Fixed formatting on all files

This commit is contained in:
Gary Mejia 2023-06-14 12:28:36 -07:00
parent b9e61f346a
commit 9a36cce7ae
3 changed files with 4 additions and 9 deletions
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6
compiler/base/rom_verilog.py
View File

@ -23,7 +23,7 @@ class rom_verilog:
self.vf.write("// OpenROM ROM model\n") self.vf.write("// OpenROM ROM model\n")
#basic info #basic info
self.vf.write("// Words: {0}\n".format(self.num_words)) self.vf.write("// Words: {0}\n".format(self.num_words))
self.vf.write("// Word size: {0}\n".format(self.word_size)) self.vf.write("// Word size: {0}\n".format(self.word_size))
self.vf.write("// Word per Row: {0}\n".format(self.words_per_row)) self.vf.write("// Word per Row: {0}\n".format(self.words_per_row))
@ -40,7 +40,7 @@ class rom_verilog:
self.gnd_name = spice["ground"] self.gnd_name = spice["ground"]
except KeyError: except KeyError:
self.gnd_name = "gnd" self.gnd_name = "gnd"
#add multiple banks later #add multiple banks later
self.vf.write("module {0}(\n".format(self.name)) self.vf.write("module {0}(\n".format(self.name))
self.vf.write("`ifdef USE_POWER_PINS\n") self.vf.write("`ifdef USE_POWER_PINS\n")
@ -88,7 +88,7 @@ class rom_verilog:
else: else:
raise ValueError(f"Data type: {self.data_type} is not supported!") raise ValueError(f"Data type: {self.data_type} is not supported!")
self.vf.write(f" end\n\n") self.vf.write(f" end\n\n")
for port in self.all_ports: for port in self.all_ports:
self.register_inputs(port) self.register_inputs(port)

5
compiler/modules/sram_1bank.py
View File

@ -25,14 +25,9 @@ class sram_1bank(design, verilog, lef):
Procedures specific to a one bank SRAM. Procedures specific to a one bank SRAM.
""" """
def __init__(self, name, sram_config): def __init__(self, name, sram_config):
print("sram_1bank debug: init")
design.__init__(self, name) design.__init__(self, name)
print("sram_1bank debug: design init")
lef.__init__(self, ["m1", "m2", "m3", "m4"]) lef.__init__(self, ["m1", "m2", "m3", "m4"])
print("sram_1bank debug: lef init")
verilog.__init__(self) verilog.__init__(self)
print("sram_1bank debug: verilog init")
self.sram_config = sram_config self.sram_config = sram_config
sram_config.set_local_config(self) sram_config.set_local_config(self)

2
compiler/rom.py
View File

@ -48,7 +48,7 @@ class rom():
import openram.modules.rom_bank as rom import openram.modules.rom_bank as rom
self.r = rom(name, rom_config) self.r = rom(name, rom_config)
self.r.create_netlist() self.r.create_netlist()
if not OPTS.netlist_only: if not OPTS.netlist_only:
self.r.create_layout() self.r.create_layout()