mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-22 06:07:31 +02:00
Do not run tapless unit tests
This commit is contained in:
@@ -25,10 +25,10 @@ class pnand2_test(openram_test):
|
||||
tx = factory.create(module_type="pnand2", size=1)
|
||||
self.local_check(tx)
|
||||
|
||||
debug.info(2, "Checking 2-input nand gate")
|
||||
tx = factory.create(module_type="pnand2", size=1, add_wells=False)
|
||||
# Only DRC because well contacts will fail LVS
|
||||
self.local_drc_check(tx)
|
||||
# debug.info(2, "Checking 2-input nand gate")
|
||||
# tx = factory.create(module_type="pnand2", size=1, add_wells=False)
|
||||
# # Only DRC because well contacts will fail LVS
|
||||
# self.local_drc_check(tx)
|
||||
|
||||
globals.end_openram()
|
||||
|
||||
|
||||
@@ -25,10 +25,10 @@ class pnand3_test(openram_test):
|
||||
tx = factory.create(module_type="pnand3", size=1)
|
||||
self.local_check(tx)
|
||||
|
||||
debug.info(2, "Checking 3-input nand gate")
|
||||
tx = factory.create(module_type="pnand3", size=1, add_wells=False)
|
||||
# Only DRC because well contacts will fail LVS
|
||||
self.local_drc_check(tx)
|
||||
# debug.info(2, "Checking 3-input nand gate")
|
||||
# tx = factory.create(module_type="pnand3", size=1, add_wells=False)
|
||||
# # Only DRC because well contacts will fail LVS
|
||||
# self.local_drc_check(tx)
|
||||
|
||||
globals.end_openram()
|
||||
|
||||
|
||||
Reference in New Issue
Block a user