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Add conditional power pins to Verilog model.

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This commit is contained in:
mrg
2021-04-30 14:15:32 -07:00
parent fc6e6e1ec7
commit 98fb34c44c
1 changed files with 11 additions and 0 deletions
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compiler/base/verilog.py
+11
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@@ -29,6 +29,11 @@ class verilog:
self.vf.write("\n")
self.vf.write("module {0}(\n".format(self.name))
self.vf.write("`ifdef USE_POWER_PINS\n")
self.vf.write(" vdd,\n")
self.vf.write(" gnd,\n")
self.vf.write("`endif\n")
for port in self.all_ports:
if port in self.readwrite_ports:
self.vf.write("// Port {0}: RW\n".format(port))
@@ -65,6 +70,12 @@ class verilog:
self.vf.write(" parameter T_HOLD = 1 ; //Delay to hold dout value after posedge. Value is arbitrary\n")
self.vf.write("\n")
self.vf.write("module {0}(\n".format(self.name))
self.vf.write("`ifdef USE_POWER_PINS\n")
self.vf.write(" inout vdd;\n")
self.vf.write(" inout gnd;\n")
self.vf.write("`endif\n")
for port in self.all_ports:
self.add_inputs_outputs(port)