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Added checks for the bitline voltage at sense amp enable 50%.

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Hunter Nichols
2018-12-12 23:59:32 -08:00
parent 0510aeb3ec
commit 97fc37aec1
4 changed files with 47 additions and 7 deletions
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technology/freepdk45/tech/tech.py
+2 -2
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@@ -328,13 +328,13 @@ spice["nand2_transition_prob"] = .1875 # Transition probability of 2-input na
spice["nand3_transition_prob"] = .1094 # Transition probability of 3-input nand.
spice["nor2_transition_prob"] = .1875 # Transition probability of 2-input nor.
#Logical Effort relative values for the Handmade cells
#Parameters related to sense amp enable timing and delay chain/RBL sizing
parameter["dff_clk_cin"] = 30.6 #relative capacitance
parameter["6tcell_wl_cin"] = 3 #relative capacitance
parameter["min_inv_para_delay"] = .5 #Tau delay units
parameter["sa_en_pmos_size"] = .72 #micro-meters
parameter["sa_en_nmos_size"] = .27 #micro-meters
parameter["rbl_height_percentage"] = .5 #Height of RBL compared to bitcell array
###################################################
##END Spice Simulation Parameters
###################################################
technology/scn4m_subm/tech/tech.py
+1
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@@ -300,6 +300,7 @@ parameter["6tcell_wl_cin"] = 2
parameter["min_inv_para_delay"] = .5
parameter["sa_en_pmos_size"] = 24*_lambda_
parameter["sa_en_nmos_size"] = 9*_lambda_
parameter["rbl_height_percentage"] = .5 #Height of RBL compared to bitcell array
###################################################
##END Spice Simulation Parameters