Added checks for the bitline voltage at sense amp enable 50%.

2026-08-29 09:30:38 +02:00 · 2018-12-12 23:59:32 -08:00
parent 0510aeb3ec
commit 97fc37aec1
4 changed files with 47 additions and 7 deletions
@@ -111,7 +111,7 @@ class control_logic(design.design):
            replica_bitline = getattr(c, OPTS.replica_bitline)
            
            delay_stages_heuristic, delay_fanout_heuristic = self.get_heuristic_delay_chain_size()
-            bitcell_loads = int(math.ceil(self.num_rows / 2.0))
+            bitcell_loads = int(math.ceil(self.num_rows * parameter["rbl_height_percentage"]))
            self.replica_bitline = replica_bitline([delay_fanout_heuristic]*delay_stages_heuristic, bitcell_loads, name="replica_bitline_"+self.port_type)
            
            if self.sram != None: