mirror of https://github.com/VLSIDA/OpenRAM.git
Flip MSB and LSB in lib file due to bug report
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cce1305da3
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@ -366,16 +366,16 @@ class lib:
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self.lib.write(" base_type : array;\n")
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self.lib.write(" data_type : bit;\n")
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self.lib.write(" bit_width : {0};\n".format(self.sram.word_size))
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self.lib.write(" bit_from : 0;\n")
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self.lib.write(" bit_to : {0};\n".format(self.sram.word_size - 1))
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self.lib.write(" bit_from : {0};\n".format(self.sram.word_size - 1))
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self.lib.write(" bit_to : 0;\n")
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self.lib.write(" }\n\n")
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self.lib.write(" type (addr){\n")
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self.lib.write(" base_type : array;\n")
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self.lib.write(" data_type : bit;\n")
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self.lib.write(" bit_width : {0};\n".format(self.sram.addr_size))
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self.lib.write(" bit_from : 0;\n")
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self.lib.write(" bit_to : {0};\n".format(self.sram.addr_size - 1))
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self.lib.write(" bit_from : {0};\n".format(self.sram.addr_size - 1))
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self.lib.write(" bit_to : 0;\n")
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self.lib.write(" }\n\n")
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if self.sram.write_size:
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@ -383,8 +383,8 @@ class lib:
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self.lib.write(" base_type : array;\n")
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self.lib.write(" data_type : bit;\n")
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self.lib.write(" bit_width : {0};\n".format(self.sram.num_wmasks))
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self.lib.write(" bit_from : 0;\n")
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self.lib.write(" bit_to : {0};\n".format(self.sram.num_wmasks - 1))
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self.lib.write(" bit_from : {0};\n".format(self.sram.num_wmasks - 1))
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self.lib.write(" bit_to : 0;\n")
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self.lib.write(" }\n\n")
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@ -887,7 +887,3 @@ class lib:
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datasheet.write("{0},{1},".format('read_rise_power_{}'.format(port), read1_power))
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#FIXME: should be read_fall_power
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datasheet.write("{0},{1},".format('read_fall_power_{}'.format(port), read0_power))
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