Clean up output file names for lvs. Update lvs script in magic.

compiler/tests/04_pbitcell_test.py

@@ -26,7 +26,7 @@ class pbitcell_test(openram_test):
         debug.info(2, "Bitcell with 1 of each port: read/write, write, and read")
         tx = pbitcell(name="pbc")
         self.local_check(tx)
-        
+
         OPTS.num_rw_ports=0
         OPTS.num_w_ports=1
         OPTS.num_r_ports=1

compiler/tests/testutils.py

@@ -13,7 +13,7 @@ class openram_test(unittest.TestCase):
 
         self.reset()
 
-        tempgds = OPTS.openram_temp + "temp.gds"
+        tempgds = "{0}{1}.gds".format(OPTS.openram_temp,w.name)
         w.gds_write(tempgds)
         import verify
 
@@ -28,8 +28,8 @@ class openram_test(unittest.TestCase):
 
         self.reset()
         
-        tempspice = OPTS.openram_temp + "temp.sp"
-        tempgds = OPTS.openram_temp + "temp.gds"
+        tempspice = "{0}{1}.sp".format(OPTS.openram_temp,a.name)
+        tempgds = "{0}{1}.gds".format(OPTS.openram_temp,a.name)
 
         a.sp_write(tempspice)
         # cannot write gds in netlist_only mode
@@ -37,7 +37,7 @@ class openram_test(unittest.TestCase):
             a.gds_write(tempgds)
 
             import verify
-            result=verify.run_drc(a.name, tempgds)
+            result=verify.run_drc(a.name, tempgds, extract=True, final_verification=final_verification)
             if result != 0:
                 #zip_file = "/tmp/{0}_{1}".format(a.name,os.getpid())
                 #debug.info(0,"Archiving failed files to {}.zip".format(zip_file))
@@ -45,7 +45,7 @@ class openram_test(unittest.TestCase):
                 self.fail("DRC failed: {}".format(a.name))
 
             
-            result=verify.run_lvs(a.name, tempgds, tempspice, final_verification)
+            result=verify.run_lvs(a.name, tempgds, tempspice, final_verification=final_verification)
             if result != 0:
                 #zip_file = "/tmp/{0}_{1}".format(a.name,os.getpid())
                 #debug.info(0,"Archiving failed files to {}.zip".format(zip_file))
@@ -54,6 +54,7 @@ class openram_test(unittest.TestCase):
 
         if OPTS.purge_temp:
             self.cleanup()
+            
 
     def find_feasible_test_period(self, delay_obj, sram, load, slew):
         """Creates a delay simulation to determine a feasible period for the functional tests to run.